P82C150AFT Philips Semiconductors, P82C150AFT Datasheet - Page 11

• Manufacturer Part Number: P82C150AFT
• Description: CAN Serial Linked I/O device SLIO with digital and analog port functions
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.2.6
This read/write register contains the bits ADC, OC3 to
OC1, M3 to M1 and SW3 to SW1 (see Fig.7).
Table 4 Analog switch selection by SW3, SW2, SW1.
Note
1. Evidently if P14 is driven, it may not be connected to
1996 Jun 19
SW3
ADC bit (analog-to-digital conversion start bit; write only
bit). The P82C150 starts an analog-to-digital conversion
cycle at ADC = 1 ended with the transmission of a
message containing the result. After that, the ADC bit is
reset automatically.
OC3 to OC1 bits (comparator output data; read only
bits). The bits OC3 to OC1 represent the logical output
level of the analog comparators at input port pins P10,
P11, P12, P13 and P15. The P82C150 sends back the
logical output value of these comparators after having
received a Data Frame (see Section 7.3.3) addressing
the Analog Configuration Register. The comparator
outputs can be monitored at the output port pins P8, P9
and P7.
M3 to M1 bits (multiplexer control bits; write only bits).
The logical value of the comparators is monitored on
port pins P8, P9 and P7 (see Fig.7) by setting M3 to M1
to logic 1, provided that these pins are configured as
outputs (OE = 1). Additionally the register content is
sent automatically when the corresponding port bits in
the Positive Edge Register and/or Negative Edge
Register and the corresponding bits in the Output
Enable Register are set.
SW3 to SW1 (analog switch control bits; write only bits).
One of the analog switches S1 to S6 can be closed by
setting the switch bits to the corresponding value
(see Fig.7 and Table 4).
CAN Serial Linked I/O device (SLIO) with
digital and analog port functions
0
0
0
0
1
1
1
1
any other driven pin via the internal analog switches
(avoid short-circuit!).
A
NALOG
SW2
0
0
1
1
0
0
1
1
C
ONFIGURATION
SW1
0
1
0
1
0
1
0
1
no switch closed (S0); note 1
S1 closed
S2 closed
S3 closed
S4 closed
S5 closed
S6 closed
reserved
R
SWITCH STATE
EGISTER
(A
DDRESS
5)
11
7.2.7
This write only register contains data for a quasi-analog
output signal on port pin P10, which is generated by
Distributed Pulse Modulation (DPM; see Fig.9).
The Output Enable bit must be set for this functions
(OE10 = 1). The DPM1 output signal is inverted by setting
DO10 = 1. The number of output pulses during a DPM
period is given by the DPM1 Register value. These pulses
have 4
period. An analog voltage is provided after smoothing the
output signal by an external RC combination.
7.2.8
This write only register contains data for a quasi-analog
output signal on port pin P4. The function of the DPM2
corresponds to the definition of DPM1.
7.2.9
This read only register contains the result of the
analog-to-digital converted level of that I/O pin which was
selected by the SW bits. The conversion is started by
ADC-bit set to logic 1 (see Section 7.2.6), or by
transmitting a Data Frame addressing the ADC Register.
DPM1 R
DPM2 R
A
R
t
CLK
NALOG-TO-
EGISTER
length and are distributed over the DPM
EGISTER
EGISTER
(A
D
DDRESS
IGITAL
(A
(A
DDRESS
DDRESS
C
8)
ONVERSION
Preliminary specification
6)
7)
P82C150
(ADC)