M36L0T7050 ST Microelectronics, M36L0T7050 Datasheet

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M36L0T7050

Manufacturer Part Number
M36L0T7050
Description
128Mbit (Multiple Bank / Multi-Level / Burst) Flash Memory 32Mbit (2M x16) PSRAM
Manufacturer
ST Microelectronics
Datasheet
FEATURES SUMMARY
FLASH MEMORY
December 2004
MULTI-CHIP PACKAGE
SUPPLY VOLTAGE
ELECTRONIC SIGNATURE
PACKAGE
SYNCHRONOUS / ASYNCHRONOUS READ
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
MEMORY ORGANIZATION
DUAL OPERATIONS
SECURITY
1 die of 128Mbit (8Mx16, Multiple Bank,
Multi-level, Burst) Flash Memory
1 die of 32Mbit (2Mx16) Pseudo SRAM
V
V
V
Manufacturer Code: 20h
Device Code (Top Flash Configuration)
M36L0T7050T0: 88C4h
Device Code (Bottom Flash
Configuration) M36L0T7050B0: 88C5h
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
Synchronous Burst Read mode: 50MHz
Asynchronous Page Read mode
Random Access: 90ns
10µs typical Word program time using
Write to Buffer and Program
Multiple Bank Memory Array: 8 Mbit
Banks
Parameter Blocks (Top or Bottom
location)
program/erase in one Bank while read in
others
No delay between read and write
operations
64 bit unique device number
2112 bit user programmable OTP Cells
DDF
DDP
PP
128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
= 9V for fast program (12V tolerant)
= 1.7 to 2V
= V
DDQ
= 2.7 to 3.3V
32Mbit (2M x16) PSRAM, Multi-Chip Package
Figure 1. Package
PSRAM
– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh
– 16 Mbit Partial Array Refresh
BLOCK LOCKING
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ACCESS TIME: 70ns
LOW STANDBY CURRENT: 100µA
DEEP POWER-DOWN CURRENT: 10µA
BYTE CONTROL: UB
PROGRAMMABLE PARTIAL ARRAY
8 WORD PAGE ACCESS CAPABILITY: 18ns
POWER-DOWN MODES
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
WP for Block Lock-Down
Absolute Write Protection with V
M36L0T7050B0
TFBGA88 (ZAQ)
M36L0T7050T0
8 x 10mm
FBGA
P
/LB
P
PP
= V
1/18
SS

M36L0T7050 Summary of contents

Page 1

... PP ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code (Top Flash Configuration) M36L0T7050T0: 88C4h – Device Code (Bottom Flash Configuration) M36L0T7050B0: 88C5h PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY SYNCHRONOUS / ASYNCHRONOUS READ – ...

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... M36L0T7050T0, M36L0T7050B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A22 Data Input/Output (DQ0-DQ15 Flash Chip Enable (E ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 F Flash Output Enable (G ) ...

Page 3

... PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline15 Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 M36L0T7050T0, M36L0T7050B0 3/18 ...

Page 4

... M36L0T7050T0, M36L0T7050B0 SUMMARY DESCRIPTION The M36L0T7050T0 and M36L0T7050B0 com- bine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M30L0T7000T0 or M30L0T7000B0, and a 32-Mbit PseudoSRAM, the M69AW048B. Recommended operating conditions do not allow more than one memory to be active at the same time. ...

Page 5

... DQ8 DQ2 DQ10 DQ5 DQ0 DQ1 DQ3 DQ12 G F DQ9 DQ11 DQ4 DDP DDQ V DDF M36L0T7050T0, M36L0T7050B0 A21 A11 K F A22 A12 A13 A20 A10 A15 A8 A14 A16 DQ13 WAIT F NC ...

Page 6

... M36L0T7050T0, M36L0T7050B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram Names, for a brief overview of the signals connect this device. Address Inputs (A0-A22). Addresses are common inputs for the Flash Memory and the PSRAM components. The other lines (A21-A22) are inputs for the Flash Memory component only. ...

Page 7

... See Measurement Load . DDF widths should be sufficient to carry the re- is both a quired V PPF M36L0T7050T0, M36L0T7050B0 is kept in a low voltage range ( seen as a control input. In this case a volt- gives an absolute protec- PPLKF is in the range acts as a power PPHF ...

Page 8

... M36L0T7050T0, M36L0T7050B0 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip En- able inputs: E for the Flash memory and for the PSRAM. P Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4 ...

Page 9

... Any PSRAM mode is allowed M36L0T7050T0, M36L0T7050B0 , Flash Data Out PSRAM must be disabled Flash Data Out PSRAM data in IH ...

Page 10

... PSRAM DEVICE The M36L0T7050T0 and M36L0T7050B0 contain a 32 Mbit PSRAM. This device can be placed in a number of sleep and partial sleep modes (see ble 3.). For detailed information on how to use the Table 3. Power-Down Configuration Data Power-Down Modes DQ15–DQ9 ...

Page 11

... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter PPFH M36L0T7050T0, M36L0T7050B0 Value Min Max –25 85 –25 85 – ...

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... M36L0T7050T0, M36L0T7050B0 DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 5. Operating and AC Measurement Conditions Parameter ...

Page 13

... I V Supply Current (Read) PP2 PPF (1) V Supply Current (Standby) I PPF PP3 Note: 1. Sampled only, not 100% tested Dual Operation current is the sum of read and program or erase currents. DD M36L0T7050T0, M36L0T7050B0 Test Condition Min DDQ OUT DDQ ...

Page 14

... M36L0T7050T0, M36L0T7050B0 Table 8. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 PPF V V Program Voltage Factory PPH PPF V Program or Erase Lockout PPLK V V Lock Voltage ...

Page 15

... SE 0.400 millimeters Min Max 1.200 0.200 0.300 0.400 7.900 8.100 0.100 9.900 10.100 – – M36L0T7050T0, M36L0T7050B0 e b ddd A2 BGA-Z42 inches Typ Min 0.0079 0.0335 0.0138 0.0118 0.3150 0.3110 0.2205 0.3937 0.3898 0.2835 0.3465 0.0315 – 0.0472 ...

Page 16

... M36L0T7050T0, M36L0T7050B0 PART NUMBERING Table 11. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage 1 DDF DDQ DDP Flash 1 Density 7 = 128 Mbit Flash 2 Density ...

Page 17

... Document status promoted from Target Specification to full Datasheet. TFBGA88 package specifications updated, package fully compliant with the ST 10-Dec-2004 1.0 ECOPACK specification. Flash memory and PSRAM data updated to the version 0.2 of the M30L0T7000x0 datasheet and to the version 5.0 of the M69AW048B datasheet. M36L0T7050T0, M36L0T7050B0 Revision Details 17/18 ...

Page 18

... M36L0T7050T0, M36L0T7050B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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