UPD62A NEC, UPD62A Datasheet - Page 26

• Manufacturer Part Number: UPD62A
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
• Manufacturer: NEC

6. RESET PIN
to GND.
246 to 694 of the system clock (f
26
PC (10 bits)
SP (1 bit)
Data
memory
Accumulator (A)
Status flag (F)
Carry flag (CY)
Timer (10 bits)
Port register
Control register P3
The system reset takes effect by inputting a low level to the RESET pin.
While the RESET pin is at low level, the system clock oscillator is stopped and the X
If the RESET pin is raised from low level to high level, it executes the program from the 0 address after counting
The RESET pin outputs a low level when the POC circuit (mask option) is in operation.
Caution When connecting a reset IC to the RESET pin, be sure to connect an IC of the N-ch open drain
Notes 1. The following resets are available.
Hardware
2. Refers to the value based on the K
R1-RF
R0 = DP
output type.
• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy
• Reset when executing the RLZ instruction (when A = 0)
• Reset by stack pointer’s overflow or underflow
In order to prevent malfunction, be sure to input a low level to more than one of pins K
reset is released (when the RESET pin changes from low level to high level, or POC is released due
to supply voltage startup).
the precondition)
P0
P1
P4
RESET
• RESET Input During Operation
• Reset by Internal POC Circuit During Operation • Reset by Internal POC Circuit in Standby
• Reset by Other Factors
000H
0B
000H
Undefined
Undefined
0B
0B
000H
FFH
03H
26H
FH
Note 2
Figure 6-1. Reset Operation by RESET Input
Operating mode or
standby mode
X
Table 6-1. Hardware Statuses After Reset
).
Data Sheet U14474EJ1V0DS00
Note 1
I
pin status.
Oscillation
stopped
(246 to 694)/f
HALT mode
• RESET Input in Standby Mode
Previous status retained
Wait
Mode
: Oscillation growth time
X
+
0 address start
Operating
mode
IN
and X
OUT
pins are fixed
I0
to K
I3
when
PD62A