GS816018BGT-150 GSI [GSI Technology], GS816018BGT-150 Datasheet

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GS816018BGT-150

Manufacturer Part Number
GS816018BGT-150
Description
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
GS816018BGT-150
Manufacturer:
LSI
Quantity:
1 200
Company:
Part Number:
GS816018BGT-150V
Quantity:
3 645
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS816018/32/36BT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
Rev: 1.03 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
operation
Flow Through
Pipeline
3-1-1-1
2-1-1-1
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
Curr
Curr
Curr
Curr
tCycle
tCycle
Parameter Synopsis
t
(x32/x36)
t
(x32/x36)
KQ
KQ
(x18)
(x18)
1/24
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS816018/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
from the internal circuits and are 3.3 V and 2.5 V compatible.
-250
295
345
225
255
2.5
4.0
5.5
5.5
-200
245
285
200
220
3.0
5.0
6.5
6.5
DDQ
GS816018/32/36BT-250/200/150
) pins are used to decouple output noise
-150
200
225
185
205
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2004, GSI Technology
250 MHz–150 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

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GS816018BGT-150 Summary of contents

Page 1

TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2 3.3 V +10%/–10% core power supply • 2 3.3 V I/O ...

Page 2

DDQ ...

Page 3

DDQ ...

Page 4

DQP DDQ ...

Page 5

TQFP Pin Description Symbol Type I ...

Page 6

Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown ...

Page 7

Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Single/Dual Cycle Deselect Control FLXDrive Output Impedance Control Note: There is a are pull-up devices on the ZQ and SCD FT pins and a pull-down device ...

Page 8

Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...

Page 9

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 10

Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B control ...

Page 11

Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles ...

Page 12

Absolute Maximum Ratings (All voltages reference Symbol Voltage in V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...

Page 13

V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...

Page 14

Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...

Page 15

DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For ...

Page 16

Operating Currents Parameter Test Conditions Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open Standby ZZ ≥ V – 0 Current Device Deselected; Deselect All other inputs Current ≥ ≤ ...

Page 17

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...

Page 18

Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.03 9/2005 Specifications cited ...

Page 19

Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...

Page 20

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...

Page 21

TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...

Page 22

... GS816032BT-200I 512K x 32 GS816032BT-150I 512K x 36 GS816036BT-250I 512K x 36 GS816036BT-200I 512K x 36 GS816036BT-150I GS816018BGT-250 GS816018BGT-200 GS816018BGT-150 512K x 32 GS816032BGT-250 512K x 32 GS816032BGT-200 512K x 32 GS816032BGT-150 512K x 36 GS816036BGT-250 512K x 36 GS816036BGT-200 512K x 36 GS816036BGT-150 GS816018BGT-250I ...

Page 23

... Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number GS816018BGT-150I 512K x 32 GS816032BGT-250I 512K x 32 GS816032BGT-200I 512K x 32 GS816032BGT-150I 512K x 36 GS816036BGT-250I 512K x 36 GS816036BGT-200I 512K x 36 GS816036BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IT. ...

Page 24

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8160xxB_r1 8160xxB_r1; 8160xxB_r1_01 8160xxB_r1_01; 8160xxB_r1_02 8160xxB_r1_02; 8160xxB_r1_03 Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • ...

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