GS816018T-225 GSI [GSI Technology], GS816018T-225 Datasheet - Page 5

• Manufacturer Part Number: GS816018T-225
• Description: 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

TQFP Pin Description
Rev: 2.12 3/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
18, 19, 22, 23, 24, 25, 28, 29
4, 11, 20, 27, 54, 61, 70, 77
47, 48, 49, 50, 43, 42
13, 12, 9, 8, 7, 6, 3, 2
75, 78, 79, 95, 96,
51, 52, 53, 56, 57
Pin Location
25, 28, 29, 30
15, 41, 65, 91
16, 38, 39, 66
51, 80, 1, 30
51, 80, 1, 30
1, 2, 3, 6, 7,
37, 36
93, 94
95, 96
98, 92
84, 85
80
87
89
88
97
86
83
64
14
31
ADSP, ADSC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Symbol
A
B
B
A
E
A9
A1
B1
C1
D1
A1
B1
V
C9
ADV
LBO
2
V
BW
GW
V
A
NC
NC
A
C
NC
0
CK
1
ZZ
FT
–A
E
DDQ
, DQ
G
, A
–DQ
–DQ
–DQ
–DQ
, DQ
–DQ
–DQ
, B
, B
, E
DD
SS
19
2
18
1
B
D
3
B9
A8
B8
C8
D8
D9
A9
B9
,
5/28
Type
I/O
I/O
I/O
—
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Address Strobe (Processor, Cache Controller); active low
GS816018/32/36T-250/225/200/166/150/133
Address field LSBs and Address Counter preset Inputs
Byte Write Enable for DQ
Byte Write Enable for DQ
Burst address counter advance enable; active low
Global Write Enable—Writes all bytes; active low
Byte Write—Writes all enabled bytes; active low
Data Input and Output pins (x32, x36 Version)
Flow Through or Pipeline mode; active low
Data Input and Output pins (x36 Version)
Data Input and Output pins (x18 Version)
Linear Burst Order mode; active low
Sleep Mode control; active high
Clock Input Signal; active high
Address Inputs (x18 versions)
Output driver power supply
No Connect (x32 Version)
No Connect (x18 Version)
Output Enable; active low
Chip Enable; active high
Chip Enable; active low
I/O and Core Ground
Core power supply
(x32, x36 Version)
Description
Address Inputs
No Connect
C
A
, DQ
, DQ
© 1999, Giga Semiconductor, Inc.
B
D
Data I/Os; active low
Data I/Os; active low
Preliminary