AM29BDS640G SPANSION [SPANSION], AM29BDS640G Datasheet
AM29BDS640G
Related parts for AM29BDS640G
AM29BDS640G Summary of contents
Page 1
Data Sheet October 1, 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
Page 2
THIS PAGE LEFT INTENTIONALLY BLANK. ...
Page 3
... Am29BDS640G 64 Megabit ( 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Data Sheet Distinctive Characteristics Architectural Advantages Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 0.17 µm process technology Enhanced VersatileIO™ — Device generates data output voltages and tolerates data input voltages as determined by the voltage on ...
Page 4
... General Description The Am29BDS640G Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 4,194,304 words of 16 bits each. This device uses a single V of 1. read, program, and erase the memory array. The device CC supports Enhanced V may be used for faster program performance if desired. The device can also be pro- grammed in standard EPROM programmers ...
Page 5
... The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. October 1, 2003 25903C1 detector that automatically in- CC Am29BDS640G , WP# locks IL 3 ...
Page 6
... Mode Read Starting at an Even Address .............................. 53 Figure 17. Reduced Wait-State Handshaking Burst Mode Read Starting at an Odd Address................................................ 54 Asynchronous Read ..............................................................................55 Figure 18. Asynchronous Mode Read with Latched Addresses . 55 Figure 19. Asynchronous Mode Read................................... 56 Figure 20. Reset Timings................................................... 57 Figure 21. Asynchronous Program Operation Timings ............ 59 Am29BDS640G 25903C1 October 1, 2003 ...
Page 7
... Figure 32. Example of Wait States Insertion (Standard Handshaking Device) ........................................................ 69 Figure 33. Back-to-Back Read/Write Cycle Timings ............... 70 Erase and Programming Performance . . . . . . . . 71 FBGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 71 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 72 FBE080—80-ball Fine-Pitch Ball Grid Array (FBGA Package ...............................................................................72 Am29BDS640G 5 ...
Page 8
... Speed Options ending in “4” and “9” indicate the “standard handshaking” option. 3. See the AC Characteristics section of this datasheet for full specifications Am29BDS640G V = 1.65 – 1. 2.7 – 3. 1.65 – 1. IACC ) IACC ) ACC Am29BDS640G 54 MHz 40 MHz D3, D4 C3, C4 D8, D9 C8, C9 87.5 95 106 120 13 13.5 20 25903C1 October 1, 2003 ...
Page 9
... State CLK Control A21–A0 October 1, 2003 25903C1 RDY Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Timer Burst Address Counter Am29BDS640G DQ15–DQ0 Input/Output Buffers Data Latch Logic Y-Decoder Y-Gating Cell Matrix X-Decoder 7 ...
Page 10
... A21–A0 A21– Bank A Address Bank A X-Decoder Bank B Address Bank B X-Decoder Status Control X-Decoder Bank C Bank C Address X-Decoder Bank D Address Bank D Am29BDS640G DQ15–DQ0 OE# DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 25903C1 October 1, 2003 ...
Page 11
... A18 A20 DQ2 DQ10 A17 A6 A5 DQ0 DQ8 CE CLK WP# AVD Am29BDS640G DQ15 DQ13 DQ6 DQ4 DQ11 DQ3 J3 K3 DQ9 DQ1 J2 ...
Page 12
... Should accelerates programming; automatically ID places device in unlock bypass mode sectors. Should A21–A0 DQ15–DQ0 CLK WP# ACC CE# OE# WE# RDY RESET# AVD# Am29BDS640G , disables IL for all other conditions. , locks all IL for all other conditions. 16 25903C1 October 1, 2003 ...
Page 13
... Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Note: For the Am29BDS640G, the last digit of the speed grade specifies the V of the device. Speed options ending in “8” and “9” (e.g., D8, D9) indicate a 1.8 Volt V range. Speed grades ending in “ ...
Page 14
... X H HIGH HIGH HIGH Z ) Control IO ) control allows the host system to set the voltage IO of 2.7 – 3.15 volts allows for I/O at the 3 volt level, driving . WE# should remain Am29BDS640G CLK (See DQ15–0 RESET# Note) AVD I/O H ...
Page 15
... ACC ) is the delay from the stable ad each burst access, what mode of burst IACC after the active edge of the first CLK cycle. Sub- IACC after the active edge of each successive clock BACC Am29BDS640G 12. 13 ...
Page 16
... See “Autoselect Com- mand Sequence” for details Table 2.) Table 2. Burst Address Groups Group Size Group Address Ranges 8 words 0-7h, 8-Fh, 10-17h, ... 16 words 0-Fh, 10-1Fh, 20-2Fh, ... 32 words 00-1Fh, 20-3Fh, 40-5Fh, ... Am29BDS640G 25903C1 October 1, 2003 ...
Page 17
... Burst Mode Configuration Register Command Se- section for more information. The device will Figure 33, “Back-to-Back Read/Write Cycle shows how read and write cycles may be initiated for simul- on this input, the device automatically enters the afore- ID Am29BDS640G , and OE and IL and OE ...
Page 18
... Note that the ACC pin must ns. The automatic sleep mode is independent of the ACC Am29BDS640G for all other conditions. IH section for more ) for read CE represents the automatic ...
Page 19
... WP# pin, the device reverts to whether the two IH , the device does not accept any write cycles. This pro- LKO power-up and power-down. The command register and all CC is greater than V CC Am29BDS640G ). If RESET# is held CC4 (not during READY after RESET# returns to Figure 20, Table 13, “Command ...
Page 20
... Alternatively, contact an sales office or representative for copies of these documents LKO , CE and OE during power up, the device does IL IH and V power-up or power-down se required during the entire V IL Am29BDS640G or WE and 25903C1 October 1, 2003 ...
Page 21
... Typical timeout per individual block erase 2 Typical timeout for full chip erase 2 Max. timeout for byte/word write 2 Max. timeout for buffer write 2 times typical N Max. timeout per individual block erase 2 Max. timeout for full chip erase 2 N Am29BDS640G Description Description µs N µ s (00h = not supported ...
Page 22
... Max. number of bytes in multi-byte write = 2 (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Am29BDS640G N 25903C1 October 1, 2003 ...
Page 23
... Bottom Boot Device, 03h = Top Boot Device Program Suspend. 00h = not supported Bank Organization Number of banks Bank A Region Information Number of sectors in bank Bank B Region Information Number of sectors in bank Bank C Region Information Number of sectors in bank Bank D Region Information Number of sectors in bank Am29BDS640G 21 ...
Page 24
... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am29BDS640G (x16) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh ...
Page 25
... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am29BDS640G (x16) Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh ...
Page 26
... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am29BDS640G (x16) Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh ...
Page 27
... Am29BDS640G (x16) Address Range 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh ...
Page 28
... Table 13, “Command Definitions,” on page 37 “Erase Suspend/Erase Resume section for more information. “Reset Command” section sections for more 18 show the timings. Am29BDS640G and “Re- 25903C1 October 1, 2003 ...
Page 29
... October 1, 2003 25903C1 Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Set Burst Mode Configuration Register Command for Command for Synchronous Mode Asynchronous Mode (A19 = 0) (A19 = 1) Synchronous Read Mode Only Table 8). Am29BDS640G 27 ...
Page 30
... Even Initial Odd Initial Odd Addr. Addr. Initial with with Addr. Boundary Boundary Am29BDS640G Total Initial Access Cycles Device Speed Rating MHz MHz 8 25903C1 October 1, 2003 ...
Page 31
... Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock October 1, 2003 25903C1 Typical No. of Clock Cycles after Table 11. Burst Read Mode Settings A16 Am29BDS640G AVD# Low 40/54 MHz ...
Page 32
... Data is valid on the 5th active CLK edge after AVD# transition to V 100 = Data is valid on the 6th active CLK edge after AVD# transition to V 101 = Data is valid on the 7th active CLK edge after AVD# transition unlock ( Am29BDS640G whenever there ...
Page 33
... BA represents the bank address, and SA represents the sector ad- dress. The device ID is read in three cycles. October 1, 2003 25903C1 shows the address and data re- Am29BDS640G 31 ...
Page 34
... IO (BA) + 0Eh 2214h (3 2234h (3 bottom boot) IO (BA) + 0Fh 2201h 0001 (locked), (SA) + 02h 0000 (unlocked) 43h (reduced wait-state), (BA) + 03h 42h (standard) Table 13 shows the address and section for information on these sta- Am29BDS640G , top boot), , top boot), 25903C1 October 1, 2003 ...
Page 35
... Table 13, “Command Definitions,” this input, the device automatically enters the Unlock ID START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Figure 2. Erase Operation Am29BDS640G for timing 33 ...
Page 36
... The system must rewrite the command se- quence and any additional addresses and commands Table 13, “Command Definitions,” on page 37 Table 13 for details on the unlock bypass com- Table 13 shows the address Am29BDS640G 25903C1 October 1, 2003 ...
Page 37
... Refer to the “Autoselect Functions” section on page 16 and “Autoselect Command Sequence” section on page 31 October 1, 2003 25903C1 43.). The time-out begins from “Write Operation Status” sec- “Write Operation Status” section for more information. Am29BDS640G sections for details. 35 ...
Page 38
... Note: See Table START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? Yes No Last Address? Yes Programming Completed for program command sequence. Figure 3. Program Operation Am29BDS640G No 25903C1 October 1, 2003 ...
Page 39
... Suspend mode, and requires the bank address. 16. See “Set Burst Mode Configuration Register Command Sequence” for details. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. , and 2214h for IO , and 2234h for 3 Am29BDS640G Fourth Fifth Addr Data Addr Data Addr (BA)X00 ...
Page 40
... Embedded Algorithm),” on page 65 shows the Data# Polling timing diagram Table 15, “Write Operation Status,” “ the AC Characteristics section Am29BDS640G 25903C1 October 1, 2003 ...
Page 41
... DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simulta- neously with DQ5. October 1, 2003 25903C1 START Read DQ7–DQ0 Addr = VA Yes DQ7 = Data DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA Yes DQ7 = Data? No FAIL Figure 4. Data# Polling Algorithm Am29BDS640G PASS 39 ...
Page 42
... Embedded Algorithm),” on page 65 Table 14, “DQ6 and DQ2 Indications,” on page (toggle bit timing diagram), and 42. Am29BDS640G “ 25903C1 October 1, 2003 ...
Page 43
... START Read DQ7–DQ0 Read DQ7–DQ0 No Toggle Bit = Toggle? Yes No DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit No = Toggle? Yes Program/Erase Operation Not Program/Erase Complete, Write Operation Complete Reset Command Figure 5. Toggle Bit Algorithm Am29BDS640G 41 ...
Page 44
... Table 14. DQ6 and DQ2 Indications then DQ6 toggles, toggles, toggles, does not toggle, returns array data, toggles, Am29BDS640G and DQ2 does not toggle. also toggles. does not toggle. toggles. returns array data. The system can read from any sector not selected for erasure. ...
Page 45
... October 1, 2003 25903C1 Table 15. Write Operation Status DQ7 (Note 2) DQ6 DQ7# Toggle 0 Toggle 1 No toggle Data Data DQ7# Toggle Am29BDS640G DQ5 DQ2 (Note 1) DQ3 (Note 2) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data ...
Page 46
... V for periods during voltage SS +0.5 V for periods ns. See CC + 2.0 V for periods ns. See +2 +0 –40°C to +85° +2.7 to +3.15 V Am29BDS640G + 0 0.5 V. During voltage Figure 7. Maximum Positive Overshoot Waveform 25903C1 October 1, 2003 ...
Page 47
... 100 µ min min I = –100 µ min min = V max CC. IH ACC Am29BDS640G Min Typ. Max max ±1 max ± 0 MHz MHz 3 0.2 10 ...
Page 48
... Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Input Measurement Level IO Am29BDS640G Table 16. Test Specifications All Speed Options Unit 0.0– ...
Page 49
... V Setup Time VIOS IO t RESET# Low Hold Time RSTH RESET# Figure 10. V October 1, 2003 25903C1 Test Setup t VCS t VIOS t RSTH and V Power-up Diagram CC IO Am29BDS640G Speed Unit Min 50 µs Min 50 µs Min 50 µs 47 ...
Page 50
... MHz) Max 120 106 Max 20 13.5 Min Min Max Max 20 13.5 Max 10 Max 10 Min Min 5 Max 20 13.5 Min Min Min Min Min Max Am29BDS640G 93 73 (40 MHz) (54 MHz) Unit 93, 94 73, 74 (40 MHz) (54 MHz) Unit 120 106 10.5 10 ...
Page 51
... The device is in synchronous mode. Figure 11. CLK Synchronous Burst Mode Read October 1, 2003 25903C1 cycles for initial access shown IACC t ACC t OE (rising active CLK) Am29BDS640G t CEZ 7 t BDH t BACC OEZ t RACC t ...
Page 52
... Figure 12. CLK Synchronous Burst Mode Read cycles for initial access shown. t CES AVD t Da IACC t ACC t t RACC OE t RDYS (Falling Active Clock) Am29BDS640G t CEZ 5 t BDH t BACC OEZ 25903C1 October 1, 2003 Hi-Z Hi-Z ...
Page 53
... IACC t ACC Figure 13. Synchronous Burst Mode Read 7 cycles for initial access shown. 18.5 ns typ. (54 MHz IACC t ACC t RACC t RDYS Am29BDS640G t CEZ BDH t BACC OEZ t RACC t RDYS t BDH t BACC ...
Page 54
... Figure 15. Burst with RDY Set One Cycle Before Data wait cycles for initial access shown typ. (40 MHz BDH t D0 IACC t ACC t RACC RDYS Am29BDS640G t CEZ t BACC OEZ 25903C1 October 1, 2003 Hi-Z Hi-Z ...
Page 55
... CLK synchronous burst mode. Figure 16. Reduced Wait-State Handshaking Burst October 1, 2003 25903C1 cycles for initial access shown IACC t ACC t OE Mode Read Starting at an Even Address Am29BDS640G t CEZ BDH t BACC OEZ t RACC ...
Page 56
... This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a CLK synchronous burst mode cycles for initial access shown IACC t ACC t OE Starting at an Odd Address Am29BDS640G t CEZ BDH t BACC OEZ t RACC t ...
Page 57
... October 1, 2003 25903C1 Max Max Max Read Toggle and Data# Polling Max OEH ACC CAS AAVDH t AVDP t AAVDS Am29BDS640G D3, D4 C3, C4 D8 Min 12 Min 5 Min 7 13.5 20 Min 0 Min 10 10 10.5 Min 0 t ...
Page 58
... AC Characteristics CE# OE# WE# DQ15-DQ0 A21-A0 AVD# Note Read Address Read Data OEH ACC RA Figure 19. Asynchronous Mode Read Am29BDS640G t OEZ Valid RD 25903C1 October 1, 2003 ...
Page 59
... October 1, 2003 25903C1 Description Readyw Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 20. Reset Timings Am29BDS640G All Speed Options Unit Max 35 µs Max 500 ns Min 500 ns Min 200 ns ...
Page 60
... AVD# or the active edge of CLK. 3. See the “Erase and Programming Performance” section for more information. 4. Does not include the preprogramming time Synchronous Asynchronous Synchronous Asynchronous Am29BDS640G All Speed Options Unit Min ...
Page 61
... The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. Figure 21. Asynchronous Program Operation Timings October 1, 2003 25903C1 AVHW t AVDP PA A0h WPH t WC Am29BDS640G Read Status Data Complete Progress t WHWH1 59 ...
Page 62
... The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. Figure 22. Alternate Asynchronous Program Operation Timings AVHW t AVDP WPH t WC Am29BDS640G Read Status Data Complete Progress t WHWH1 25903C1 October 1, 2003 ...
Page 63
... CLK must not have an active edge while WE AVD# must toggle during command sequence unlock cycles. Figure 23. Synchronous Program Operation Timings October 1, 2003 25903C1 WPH Am29BDS640G Read Status Data Complete Progress t WHWH1 61 ...
Page 64
... CLK must not have an active edge while WE Figure 24. Alternate Synchronous Program Operation Timings (Note 8) AVDP PA A0h WPH Am29BDS640G Read Status Data Complete Progress t WHWH1 25903C1 October 1, 2003 ...
Page 65
... Address bits A21–A12 are don’t cares during unlock cycles in the command sequence. October 1, 2003 25903C1 555h for 10h for chip erase chip erase 30h WPH t WC Am29BDS640G Read Status Data Complete Progress t WHWH2 63 ...
Page 66
... ACC Note: Use setup and hold times from conventional program operation. Figure 26. Accelerated Unlock Bypass Programming Timing Don't Care A0h Don't Care VIDS t VID Am29BDS640G PA PD Don't Care 25903C1 October 1, 2003 ...
Page 67
... AVD# must toggle between data reads. Figure 28. Toggle Bit Timings (During Embedded Algorithm) October 1, 2003 25903C1 CEZ t OEZ Status Data Status Data Am29BDS640G VA Status Data t VA Status Data CEZ t OEZ 65 ...
Page 68
... RDY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1 in the Burst Mode Configuration Register, RDY is active one clock cycle before data. 4. AVD# must toggle between data reads. Figure 29. Synchronous Data Polling Timings IACC Status Data Toggle Bit Timings Am29BDS640G t IACC Status Data 25903C1 October 1, 2003 ...
Page 69
... Figure 30. Latency with Boundary Crossing October 1, 2003 25903C1 C62 C63 C63 C63 RACC latency t t RACC RACC latency D61 D62 D63 Am29BDS640G C64 C65 C66 RACC D64 D65 D66 C67 43 D67 67 ...
Page 70
... Figure 31. Latency with Boundary Crossing C62 C63 C63 C63 RACC latency t t RACC RACC latency D61 D62 D63 into Program/Erase Bank Am29BDS640G C64 RACC Invalid Read Status 25903C1 October 1, 2003 ...
Page 71
... October 1, 2003 25903C1 total number of clock cycles following AVD# falling edge number of clock cycles programmed Am29BDS640G D0 D1 Rising edge of next clock cycle following last wait state triggers next burst data ...
Page 72
... Read status (at least two cycles) in same bank and/or array data from other bank OEH t OEZ t ACC t t OEH SR Am29BDS640G Begin another write or program command sequence GHWL RD AAh 555h 25903C1 October 1, 2003 ...
Page 73
... V, 1,000,000 cycles. CC Test Setup Test Conditions 150°C 125°C Am29BDS640G Unit Comments s Excludes 00h programming prior to erasure (Note 4) s Excludes system level µs overhead (Note 5) µs Excludes system level s overhead (Note 1 million cycles. Additionally, ...
Page 74
... BALL PITCH OUTER ROW e/2 8. "+" IN THE PACKAGE DRAWING INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 FOR PACKAGE THICKNESS, "A" IS THE CONTROLLING DIMENSION CORNER TO BE IDENTIFIED BY CHAMFER, INK MARK, METALLIZED MARKINGS INDENTION OR OTHER MEANS. Am29BDS640G ...
Page 75
... Added note to indicate AVD# must toggle during data reads. Figures 30, 31 Shifted address, clock, and data cycle counts up by one. October 1, 2003 25903C1 ACC to test conditions for V and CSW1 CSW2 CHW to 21. Am29BDS640G in table AHC 73 ...
Page 76
... Replaced addresses “XXX” with “BA” in first and second cycles of Sector Lock/Un- lock table row. Modified description legend time. CHW to t and added t AHW AVSW CSW2 . Removed t . AVHC ACH switched Typ. and Max. values Am29BDS640G CC . 25903C1 October 1, 2003 ...
Page 77
... Revision (October 1, 2003) DC Characteristics - CMOS Compatible Added note #2. Modified column heading from Test Conditions (Note 1) to Test Conditions (Note 1,2) October 1, 2003 25903C1 Am29BDS640G 75 ...
Page 78
... FASL. The information in this document is subject to change without notice. Product and Company names are trademarks or registered trademarks of their respective owners Copyright 2003 FASL LLC. All rights reserved Am29BDS640G 25903C1 October 1, 2003 ...