AM29BDS640G SPANSION [SPANSION], AM29BDS640G Datasheet - Page 29

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AM29BDS640G

Manufacturer Part Number
AM29BDS640G
Description
64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
Manufacturer
SPANSION [SPANSION]
Datasheet
October 1, 2003 25903C1
Read Mode Setting
On power-up or hardware reset, the device is set to be in asynchronous read
mode. This setting allows the system to enable or disable burst mode during sys-
tem operations. Address A19 determines this setting: “1’ for asynchronous mode,
“0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock
cycles that must elapse after AVD# is driven active before data will be available.
This value is determined by the input frequency of the device. Address bits A14–
A12 determine the setting (see
The wait state command sequence instructs the device to set a particular number
of clock cycles for the initial access in burst mode. The number of wait states that
should be programmed into the device is directly related to the clock frequency.
Figure 1. Synchronous/Asynchronous State Diagram
Configuration Register
P r e l i m i n a r y
Synchronous Mode
Set Burst Mode
Command for
(A19 = 0)
Asynchronous Read
Table
Synchronous Read
Am29BDS640G
Hardware Reset
Power-up/
Mode Only
Mode Only
8).
Configuration Register
Asynchronous Mode
Set Burst Mode
Command for
(A19 = 1)
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