VRS51C1000-40-L RAMTRON [Ramtron International Corporation], VRS51C1000-40-L Datasheet - Page 29

• Manufacturer Part Number: VRS51C1000-40-L
• Description: Versa 8051 MCU with 64KB of IAP/ISP Flash
• Manufacturer: RAMTRON [Ramtron International Corporation]

Interrupts
The VRS51C1000 has 8 interrupt sources (9 if we
include the WDT) and 7 interrupt vectors (including
reset) for handling.
The interrupts are enabled via the IE register shown
below:
T
The following figure illustrates the various interrupt
sources on the VRS51C1000.
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F
ABLE
IGURE
5
4
3
2
1
0
Bit
7
6
EXF2
VRS51C1000
INT0
INT1
EA
TF0
TF1
7
TF2
T1
RI
32: IE I
20: I
ET2
ES
ET1
EX1
ET0
EX0
Mnemonic
EA
-
NTERRUPT
NTERRUPT
6
-
IT0
IT1
S
E
OURCES
ET2
NABLE
5
Description
Disables All Interrupts
0: no interrupt acknowledgment
1: Each interrupt source is individually
enabled or disabled by setting or clearing
its enable bit.
Reserved
Timer 2 Interrupt Enable Bit
Serial Port Interrupt Enable Bit
Timer 1 Interrupt Enable Bit
External Interrupt 1 Enable Bit
Timer 0 Interrupt Enable Bit
External Interrupt 0 Enable Bit
R
EGISTER
ES
4
IE0
IE1
–SFR A8
ET1
3
H
EX1
2
INTERRUPT
SOURCES
ET0
1
EX0
0
Interrupt Vectors
The following table specifies each interrupt source, its
flag and its vector address.
T
*If location 0000h = FFh, the PC jump to the ISP program.
External Interrupts
The VRS51C1000 has two external interrupt inputs
(INT0 and INT1). These interrupt lines are shared with
the P3.2 and P3.3 I/Os.
Bits IT0 and IT1 of the TCON register determine
whether the external interrupts are level or edge
sensitive.
If ITx = 1, the interrupt will be raised when a 1 to 0
transition occurs at the interrupt pin. The duration of
the transition must be at least equal to 12 oscillator
cycles.
If ITx = 0, the interrupt will occur when a logic low
condition is present on the interrupt pin.
The state of the external interrupt, when enabled, can
be monitored using the flags, IE0 and IE1 of the TCON
register and will be set when the interrupt condition
occurs.
In the case where the interrupt was configured as edge
sensitive, the associated flag is automatically cleared
when the interrupt is serviced.
If the interrupt is configured as level sensitive, then the
interrupt flag must be cleared by the software.
ABLE
RESET (+ WDT)
INT0
Timer 0
INT1
Timer 1
Serial Port
Timer 2
Interrupt Source
33: I
NTERRUPT
V
ECTOR
A
DDRESS
WDR
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
Flag
page 29 of 48
Address
0000h*
Vector
000Bh
001Bh
002Bh
0003h
0013h
0023h