GS8161Z18 GSI [GSI Technology], GS8161Z18 Datasheet - Page 23
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GS8161Z18
Manufacturer Part Number
GS8161Z18
Description
18Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS8161Z18.pdf
(36 pages)
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JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
drivers are powered by V
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
Rev: 2.15 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A0–An
CKE
ADV
DQ
CK
Bn
W
G
E
tS
tS
tS
tS
tS
tS
A
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
Write A
DDQ
tH
tH
tH
tH
tH
tH
.
D(A)
tS
B
Write B
tH
D(B)
Write B+1
tKH
tKH
Flow Through Mode Timing
tKL
tKL
D(B+1)
C
23/36
tLZ
Read C
tKQ
tKC
tKC
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Q(C)
Cont
DD
tOHZ
or V
D
SS
Read D
. TDO should be left unconnected.
tOE
tOLZ
E
Q(D)
Write E
tHZ
tKQX
DD
F
D(E)
. The JTAG output
tLZ
Read F
tKQ
© 1998, GSI Technology
Q(F)
G
Write G
tKQX
D(G)