HY27UG088GDM HYNIX [Hynix Semiconductor], HY27UG088GDM Datasheet - Page 24
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HY27UG088GDM
Manufacturer Part Number
HY27UG088GDM
Description
8Gbit (1Gx8bit) NAND Flash
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.HY27UG088GDM.pdf
(50 pages)
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Rev. 0.6 / Dec. 2006
CLE Setup time
CLE Hold time
CE setup time
CE hold time
WE pulse width
ALE setup time
ALE hold time
Data setup time
Data hold time
Write Cycle time
WE High hold time
Address to Data Loading Time
Data Transfer from Cell to register
ALE to RE Delay
CLE to RE Delay
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
RE Access Time
RE High to Output High Z
CE High to Output High Z
Cache read RE High
RE High to Output Hold
RE Low to Output Hold
CE High to Output Hold
RE High Hold Time
Output High Z to RE low
CE Access Time
WE High to RE low
Device Resetting Time
(Read / Program / Copy-Back Program / Erase)
Write Protection time
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
3. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
Parameter
Table 12: AC Timing Characteristics
Symbol
tRHOH
tADL
tCRRH
tRLOH
tWW
tWHR
tCOH
tREA
tRHZ
tCHZ
tREH
tCLH
tALH
tCLR
tCEA
tRST
tCLS
tALS
tWH
tWP
tWC
tWB
tCH
tDH
tCS
tDS
tAR
tRR
tRP
tRC
tIR
tR
(3)
(2)
8Gbit (1Gx8bit) NAND Flash
HY27UG088G(5/D)M Series
Min
100
100
100
15
25
15
15
15
30
10
15
15
20
15
30
15
15
10
60
5
5
5
5
5
0
3.3Volt
5/10/40/500
Max
100
25
25
50
50
30
(1)
Unit
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
24
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