EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet - Page 14

• Manufacturer Part Number: EVAL-ADAU1701EB
• Description: SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
• Manufacturer: AD [Analog Devices]

ADAU1701
INITIALIZATION
POWER-UP SEQUENCE
The ADAU1701 has a built-in power-up sequence that
initializes the contents of all internal RAMs on power-up or
when the part is brought out of reset. After RESETB (positive
edge-triggered) goes high, the contents of the internal program
boot ROM are copied to the internal program RAM memory,
the parameter RAM (all zeros) is filled with values from its
associated boot ROM, and all registers are initialized to all-
zeros. The default boot ROM program simply copies inputs to
outputs with no processing (Figure 15). In this program, serial
digital inputs 0-1 are output on DACs 0-1 and serial digital
outputs 0-1. ADCs 0-1 are output on DACs 2-3. The data
memories are also zeroed at power-up. New values should not
be written to the control port until the initialization is complete.
Table 12. Power-up time
MCLKI input
3.072 MHz (64 × fs)
11.289 MHz (256 × fs)
12.288 MHz (256 × fs)
18.432 MHz (384 × fs)
24.576 MHz (512 × fs)
The PLL start-up time lasts for 2
MCLKI pin. This time will range from 10.7 ms for a 24.576
MHz (512 × fs) input clock to 85.3 ms for a 3.072 MHz (64 × fs)
input clock. This start-up time is measured from the rising edge
of RESETB. Following the PLL start-up the ADAU1701’s boot
cycle takes 2048 cycles of the internal master clock (49.152
MHz at f
reading from the ADAU1701 during this start-up time. For a
12.288 MHz input MCLK, the full initialization sequence (PLL
start-up plus boot cycle) will last approximately 22 ms. Coming
out of reset, the clock mode is immediately set by the
PLL_MODE0 and PLL_MODE1 pins. Reset is synched to the
falling edge of the internal MCLK.
Table 12 shows examples of typical times to boot the
ADAU1701 into an application’s operational state, assuming a
400 kHz I
registers (8.5 kB). In reality, most applications will use less than
this full amount, so the boot time (column 3) will be shorter.
RECOMMENDED PROGRAM/PARAMETER
LOADING PROCEDURE
When writing large amounts of data to the program or
parameter RAM in direct write mode, the processor core should
be disabled to prevent unpleasant noises from appearing at the
audio output.
s
= 48 kHz). The user should avoid writing to or
2
C clock loading a full program, parameter set, and all
Init. time
85 ms
23 ms
21 ms
16 ms
11 ms
18
cycles of the clock on the
Maximum
Program/
Parameter/
Register Boot
Time (I
175 ms
175 ms
175 ms
175 ms
175 ms
2
C)
Total
260 ms
198 ms
196 ms
191 ms
186 ms
Rev. PrF | Page 14 of 43
1.
2.
3.
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5.
POWER REDUCTION MODES
Sections of the ADAU1701 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
DACs, and voltage reference.
The individual analog sections can be turned off in the
Auxiliary ADC & Power Control Register (2082). By default,
the ADCs, all four DACs, and reference are enabled (all bits set
to 0). Each of these can be turned off by writing a 1 to the
appropriate bits in this register. The ADC power-down mode
will power down both ADCs and each DAC can be powered
down individually. The current savings will be about 15 mA
when the ADCs are powered down, and about 4 mA for each
powered-down DAC. The voltage reference, which is supplied
to both the ADCs and DACs, should only be powered down if
the ADCs and all four DACs are also powered down. The
reference is powered down by setting both bits 6 and 7 of the
control register.
USING THE OSCILLATOR
The ADAU1701 has an on-board oscillator that can be used to
generate the part’s master clock. The oscillator is designed to
work with a 256 × f
SD ATA_IN 0
Assert bits 3 and 4 (active low) of the core control register
to mute the ADCs and DACs. This begins a volume ramp-
down.
Assert bit 2 (active low) of the core control register. This
zeroes the SigmaDSP’s accumulators, the data output
registers, and the data input registers.
Fill the program RAM using burst-mode writes.
Fill the parameter RAM using burst-mode writes.
Deassert bits 2-4 of the core control register.
ADC0
ADC1
Figure 15. Default Program Signal Flow
s
Preliminary Technical Data
master clock, which will be 12.288 MHz for
DAC0
DAC1
DAC2
DAC3
SD ATA_OUT 0