EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet - Page 21

• Manufacturer Part Number: EVAL-ADAU1701EB
• Description: SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Subaddress
The 12-bit Subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. In burst write mode, an initial
subaddress is given followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
(CONTINUED)
(CONTINUED)
(CONTINUED)
(CONTINUED)
SCK
SDA
SDA
START BY
SCK
(CONTINUED)
SDA
MASTER
SCK
(CONTINUED)
SCK
SDA
START BY
MASTER
SCK
SDA
0
0
CHIP ADDRESS BYTE
0
SUBADDRESS BYTE 2
CHIP ADDRESS BYTE
READ DATA BYTE 1
SUBADDRESS BYTE 2
FRAME 1
FRAME 3
FRAME 5
0
FRAME 1
FRAME 2
0
0
Figure 22. ADAU1701 I2C Write Clocking
ADR
Figure 23. ADAU1701 I
SEL
ADR
SEL
R/W
Rev. PrF | Page 21 of 43
R/W
ADAU1701
ADAU1701
ACK. BY
MASTER
ACK. BY
ACK. BY
ADAU1701
ADAU1701
ACK. BY
ACK. BY
REPEATED
START BY
MASTER
2
C Read Clocking
format diagram for continuous-mode operation is given in the
Control Port Read/Write Data Formats section.
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 28. A sample timing
diagram of a single SPI read operation is shown in Figure 29.
The COUT pin goes from three-state to driven at the beginning
of Byte 3. In this example, Bytes 0 to 2 contain the addresses and
R/W bit, and subsequent bytes carry the data.
SUBADDRESS BYTE 1
READ DATA BYTE 2
SUBADDRESS BYTE 1
FRAME 6
DATA BYTE 1
FRAME 2
CHIP ADDRESS BYTE
FRAME 3
FRAME 2
FRAME 4
ADAU1701
MASTER
ACK. BY
ACK. BY
ADAU1701
ADR
SEL
ADAU1701
ACK. BY
ACK. BY
ADAU1701
R/W
STOP BY
MASTER
ACK. BY
ADAU1701
STOP BY
MASTER