EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet - Page 28

• Manufacturer Part Number: EVAL-ADAU1701EB
• Description: SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
• Manufacturer: AD [Analog Devices]

ADAU1701
DSP CORE CONTROL REGISTER
The controls in this register set the operation of the
ADAU1701’s DSP core.
Table 26. DSP Core Control Register (2076)
Register Bits
15:14
13:12
11:9
8
7
6
5
4
3
2
1:0
GPIO Debounce control (Bits 13:12)
Set debounce time of multipurpose pins set as GPIO inputs.
Aux ADC Data registers control port write mode (Bit 8)
Setting this bit allows data to be written directly to the Aux
ADC Data registers (2057-2060) from the control port. When
set, the Aux ADC Data registers will no longer respond to
settings on the multi-purpose pins.
GPIO Pin Setting register control port write mode (Bit 7)
When this bit is set, the GPIO Pin Setting register (2056) can be
written to directly from the control port and this register will no
longer respond to input settings on the multi-purpose pins.
Interface registers control port write mode (Bit 6)
When this bit is set, data can be written directly to the Interface
registers (2048-2055) from the control port. In that state, the
Interface registers will not be written from the SigmaDSP
program.
Initiate Safe Transfer to Parameter RAM (Bit 5)
Setting this bit to 1 initiates a safeload transfer to the parameter
RAM. This bit is automatically cleared when the operation is
completed. There are five safeload register pairs (address/data);
only those registers that have been written since the last
safeload event are transferred to the parameter RAM.
Function
Reserved
GPIO Debounce control
00 = 20ms
01 = 40ms
10 = 10ms
11 = 5ms
Reserved
Aux ADC Data registers control port write mode
GPIO Pin Setting register control port write
mode
Interface registers control port write mode
Initiate Safeload Transfer
Mute ADCs, active low
Mute DACs, active low
Clear Internal Registers to All Zeros, active low
Sample Rate
00 = 1× (1024 instructions, 48 kHz)
01 = 2× (512 instructions, 96 kHz)
10 = 4× (256 instructions, 192 kHz)
00 = reserved
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Mute ADCs (Bit 4)
This bit will mute the output of the ADCs. The bit defaults to 0
and is active-low, so it must be set to 1 in order to pass audio
from the ADCs.
Mute DACs (Bit 3)
This bit will mute the output of the DACs. The bit defaults to 0
and is active-low, so it must be set to 1 in order to pass audio
from the DACs.
Clear Internal Registers to All Zeros (Bit 2)
This bit defaults to 0 and is active low. This bit needs to be set to
1 in order for a signal to pass through the SigmaDSP core.
Sample Rate (Bits 1:0)
These bits set the number of DSP instructions for every sample
and the sample rate at which the ADAU1701 will operate. At the
default setting of 1× there will be 1024 instructions per audio
sample. This setting should be used with sample rates such as
48 kHz and 44.1 kHz.
In the 2× setting the number of instructions per frame will be
halved to 512 and the ADCs and DACs will nominally run at a
96 kHz sample rate.
At a 4× setting there will be 256 instructions per cycle and the
converters will run at a 192 kHz sample rate.
INTERFACE REGISTERS
The interface registers are used in self-boot mode to save
parameters that need to be written to the external EEPROM.
The ADAU1701 will then recall these parameters from the
EEPROM after the next reset or power-up. This way, system
parameters such as volume and EQ settings can be saved during
power-down and recalled when the system is next turned on.
There are eight 32-bit interface registers, which allows for eight
28-bit (plus zero-padding) parameters to be saved. The
parameters that will be saved in these registers are set in the
graphical programming tools. These registers are updated with
their corresponding parameter RAM data once per sample
period.
An edge, which can be set to be either rising or falling, triggers
the ADAU1701 to write the current contents of the interface
registers to the EEPROM. See more information in the Self boot
section.
The user can write directly to the interface registers after bit 6 in
the DSP core control register has been set. In this mode, the
data in the registers is written from the control port and not
from the DSP core.
CONTROL PORT READ/WRITE DATA FORMATS
The read/write formats of the control port are designed to be
byte-oriented. This allows for easy programming of common
Preliminary Technical Data