AM29F400B AMD [Advanced Micro Devices], AM29F400B Datasheet - Page 7

• Manufacturer Part Number: AM29F400B
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
Legend:
L = Logic Low = V
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and control-
led by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at V
device outputs array data in words or bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary Sector Unprotect
(See Note)
Read
Operation
IH
. The BYTE# pin determines whether the
IL
, H = Logic High = V
V
0.5 V
CE#
CC
Table 1. Am29F400B Device Bus Operations
H
L
L
L
X
X
IL
. CE# is the power
±
IH
, V
ID
OE#
H
X
X
H
X
X
L
= 12.0 0.5 V, X = Don’t Care, D
WE#
P R E L I M I N A R Y
H
H
X
X
X
X
L
Am29F400B
RESET#
V
0.5 V
V
CC
H
H
H
H
L
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 9 for the timing diagram. I
DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more in-
formation.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad-
dress” consists of the address bits required to uniquely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
ID
±
IL
A0–A17
, and OE# to V
IN
A
A
A
X
X
X
X
= Data In, D
IN
IN
IN
DQ0–DQ7
OUT
High-Z
High-Z
High-Z
High-Z
D
IH
D
D
OUT
.
IN
IN
= Data Out, A
BYTE#
High-Z
High-Z
High-Z
High-Z
D
= V
D
D
OUT
DQ8–DQ15
IN
IN
IN
IH
= Address In
CC1
BYTE#
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
= V
in the
IL
7