AM29LV400 AMD [Advanced Micro Devices], AM29LV400 Datasheet

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AM29LV400

Manufacturer Part Number
AM29LV400
Description
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
Manufacturer
AMD [Advanced Micro Devices]
Datasheet

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Am29LV400
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
— Regulated voltage range: 3.0 to 3.6 volt read
High performance
— Full voltage range: access times as fast as 100
— Regulated voltage range: access times as fast
Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 10 mA read current
— 20 mA program/erase current
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
— One 8 Kword, two 4 Kword, one 16 Kword, and
— Supports full chip erase
— Sector Protection features:
operations for battery-powered applications
and write operations and for compatibility with
high performance 3.3 volt microprocessors
ns
as 90 ns
seven 64 Kbyte sectors (byte mode)
seven 32 Kword sectors (word mode)
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
PRELIMINARY
Top or bottom boot block configurations
available
Embedded Algorithms
— Embedded Erase algorithm automatically
— Embedded Program algorithm automatically
Typical 1,000,000 write cycles per sector
(100,000 cycles minimum guaranteed)
Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
Compatibility with JEDEC standards
— Pinout and software compatible with single-
— Superior inadvertent write protection
Data# Polling and toggle bits
— Provides a software method of detecting
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
preprograms and erases the entire chip or any
combination of designated sectors
writes and verifies data at specified addresses
power supply Flash
program or erase operation completion
program or erase cycle completion
or program data to, a sector that is not being
erased, then resumes the erase operation
array data
Publication# 20514
Issue Date: March 1998
Rev: C Amendment/+1

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AM29LV400 Summary of contents

Page 1

... PRELIMINARY Am29LV400 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3 ...

Page 2

... GENERAL DESCRIPTION The Am29LV400 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system using only a single 3 ...

Page 3

... CC = 2.7–3 Sector Switches Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer X-Decoder Am29LV400 Am29LV400 -100 -120 -150 100 120 150 100 120 150 – DQ0 DQ15 (A-1) Input/Output Buffers Data STB Latch ...

Page 4

... CC 13 DQ11 14 DQ3 DQ10 15 16 DQ2 17 DQ9 18 DQ1 19 DQ8 20 DQ0 Standard TSOP Reverse TSOP Am29LV400 48 A16 47 BYTE DQ15/A-1 44 DQ7 43 DQ14 42 DQ6 41 DQ13 40 DQ5 39 DQ12 38 DQ4 DQ11 35 DQ3 ...

Page 5

... A17 A6 A5 DQ0 DQ2 DQ5 A10 A11 DQ7 A12 A14 A15 A16 Am29LV400 44 RESET A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BYTE DQ15/A-1 30 DQ7 29 DQ14 28 DQ6 ...

Page 6

... compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time. LOGIC SYMBOL 18 A0–A17 CE# OE# WE# RESET# BYTE# Am29LV400 DQ0–DQ15 (A-1) RY/BY# 20514C-4 6 ...

Page 7

... EC, EI, FC, Am29LV400B70R FI, SC, SI, WAC Am29LV400T80, Am29LV400B80 EC, EI, EE, Am29LV400T90, FC, FI, FE, Am29LV400B90 SC, SI, SE, WAC, WAI, WAE Am29LV400T120, Am29LV400B120 OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0°C to +70° Industrial (– ...

Page 8

... The command register itself does not occupy any addressable memory location. The register is composed of latches that store the com- mands, along with the address and data information needed to execute the command. The contents of the Table 1. Am29LV400 Device Bus Operations Operation CE# OE# WE# RESET# Read ...

Page 9

... The system can read data t SET# pin returns to V Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 13 for the timing diagram. Output Disable Mode When the OE# input Am29LV400 in the DC Characteristics table CC4 RP ±0.3 V, the device RESET# is held CC4 ± ...

Page 10

... Table 2. Am29LV400T Top Boot Block Sector Address Table Sector A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Table 3. Am29LV400B Bottom Boot Block Sector Address Table ...

Page 11

... When using programming equipment, the autoselect mode requires V (11 12 address pin ID A9. Address pins A6, A1, and A0 must be as shown in Table 4. Am29LV400 Autoselect Codes (High Voltage Method) Description Mode CE# Manufacturer ID: AMD L Device ID: ...

Page 12

... Power-Up Write Inhibit If WE device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. Am29LV400 CC Write Inhibit is less than V , the device does not ac- LKO . The system must provide the ...

Page 13

... When the Embedded Program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits. Am29LV400 ...

Page 14

... The time be- tween these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin recommended that processor interrupts be disabled during this time to Am29LV400 14 ...

Page 15

... The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the de- Am29LV400 ...

Page 16

... Command Sequence Data Poll from System No Data = FFh? Yes Erasure Completed Notes: 1. See Table 5 for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information. Figure 3. Erase Operation Embedded Erase algorithm in progress 20514C-7 Am29LV400 16 ...

Page 17

... Table 5. Am29LV400 Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector Protect Verify 4 (Note 9) Byte Word Program 4 Byte Word ...

Page 18

... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 4. Data# Polling Algorithm Am29LV400 Yes Yes PASS 20514C-8 18 ...

Page 19

... DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. Am29LV400 ...

Page 20

... Complete, Write Reset Command Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1” . See text. Figure 5. Toggle Bit Algorithm Am29LV400 (Note 1) No (Notes Program/Erase Operation Complete ...

Page 21

... DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details Table 6. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 0 Toggle toggle 0 Data Data Data DQ7# Toggle 0 Am29LV400 DQ2 DQ3 (Note 2) RY/BY# N/A No toggle 0 1 Toggle 0 N/A Toggle 1 Data Data 1 N/A N/A 0 ...

Page 22

... Operating ranges define those limits between which the func- tionality of the device is guaranteed +0.8 V –0.5 V –2 Figure 6. Maximum Negative Overshoot +0 Figure 7. Maximum Positive Overshoot Am29LV400 20514C-10 Waveform 20514C-11 Waveform 22 ...

Page 23

... 4.0 mA min I = –2 min I = –100 min . Typical Am29LV400 Min Typ Max Unit –0.5 0 ...

Page 24

... Figure 8. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note 1500 2000 2500 Time Frequency in MHz Figure 9. Typical I vs. Frequency CC1 Am29LV400 3000 3500 4000 20514C- 20514C-13 24 ...

Page 25

... Input timing measurement reference levels Output timing measurement reference levels 20514C-14 INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am29LV400 -90R, -120, -100 -150 Unit 1 TTL gate L 30 100 0.0– ...

Page 26

... OE OE Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 12. Read Operations Timings Am29LV400 Speed Option -90R -100 -120 -150 Min 90 100 120 150 Max 90 100 120 150 Max 90 100 120 150 ...

Page 27

... Test Setup Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 13. RESET# Timings Am29LV400 All Speed Options Max 20 Max 500 Min 500 Min 50 Min 20 Min 20514C-17 ...

Page 28

... Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am29LV400 -100 -120 -150 Unit 100 120 150 ns Data Output (DQ0–DQ7) Address Input 20514C-18 20514C-19 28 ...

Page 29

... -90R Min 90 Min Min 50 Min 50 Min Min Min Min Min Min 50 Min 30 Byte Typ Word Typ Typ Min Min Min Am29LV400 -100 -120 -150 Unit 100 120 150 ...

Page 30

... Illustration shows device in word mode WPH A0h t BUSY is the true data at the program address. OUT Figure 16. Program Operation Timings Am29LV400 Read Status Data (last two cycles WHWH1 Status D OUT t RB 20514C-20 30 ...

Page 31

... SA = sector address (for Sector Erase Valid Address for reading status data (see “Write Operation Status”). 2. Illustration shows device in word mode. Figure 17. Chip/Sector Erase Operation Timings 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am29LV400 Read Status Data WHWH2 In Complete Progress t RB 20514C-21 ...

Page 32

... Complement Complement Status Data Status Data Valid Status Valid Status (first read) (second read) Am29LV400 VA True Valid Data Valid Data True 20514C- Valid Status Valid Data (stops toggling) 20514C-23 High Z High Z 32 ...

Page 33

... Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 20. DQ2 vs. DQ6 Min Min Program or Erase Command Sequence t RSP Am29LV400 Erase Resume Erase Erase Complete Read 20514C-24 All Speed Options 500 VIDR ...

Page 34

... See the “Erase and Programming Performance” section for more information -90R Min 90 Min Min 50 Min 50 Min Min Min Min Min Min 50 Min 30 Byte Typ Word Typ Typ Am29LV400 -100 -120 -150 Unit 100 120 150 ...

Page 35

... PA for program SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase Am29LV400 PA DQ7# D OUT = data written to the OUT 20514C-26 ...

Page 36

... V, 100,000 cycles. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT V IN Test Conditions 150 C 125 C Am29LV400 Unit Comments s Excludes 00h programming prior to erasure (Note Excludes system level overhead (Note 100,000 cycles. Additionally, CC Min Max –1.0 V 12.5 V –1 ...

Page 37

... TSR048—48-Pin Reverse TSOP (measured in millimeters) Pin 1 I. 1.20 MAX 0.25MM (0.0098") BSC * For reference only. BSC is an ANSI standard for Basic Space Centering 18.30 18.50 19.80 20.20 0˚ 5˚ 0.50 0. 18.30 18.50 19.80 20.20 0˚ 5˚ 0.50 0.70 Am29LV400 0.95 1.05 11.90 12.10 0.50 BSC 0.05 0.15 16-038-TS48-2 0.08 TS 048 0.20 DT95 8-8-96 lv 0.10 0.21 0.95 1.05 11.90 12.10 0.50 BSC 0.05 0.15 SEATING PLANE 16-038-TS48 TSR048 0.08 DT95 0.20 8-8-96 lv ...

Page 38

... PHYSICAL DIMENSIONS Fine-Pitch Ball Grid Array (FBGA) (measured in millimeters) DATUM B 0.025 CHAMFER INDEX 0.80 0.40 0.08 (48x) 0. 0.25 0.45 1.20 MAX 0. 7.80 8.20 DATUM A 5.60 BSC 0.40 DETAIL A 0.20 Z DETAIL A Am29LV400 5.80 0. 6.20 0.40 4.00 BSC 0.10 Z 16-038-FGA-2 EG137 12-2- ...

Page 39

... PHYSICAL DIMENSIONS SO 044—44-Pin Small Outline Package (measured in millimeters 1.27 NOM. TOP VIEW 28.00 28.40 2.17 2.45 0.35 0.50 SIDE VIEW 13.10 15.70 13.50 16.30 22 2.80 MAX. SEATING PLANE 0.10 0.35 Am29LV400 0.10 0.21 0˚ 0.60 8˚ 1.00 END VIEW 16-038-SO44-2 SO 044 DF83 8-8-96 lv ...

Page 40

... REVISION SUMMARY FOR AM29LV400 Revision C Added FBGA package. Formatted for consistency with other current 5.0 volt-only data sheets. Revision C+1 DC Characteristics Changed Note 1 to indicate that OE# should Characteristics Erase/Program Operations; Alternate CE# Controlled Erase/Program Operations: Corrected the notes refer- ence for t and t ...

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