AM29LV641GH53R SPANSION [SPANSION], AM29LV641GH53R Datasheet - Page 12

• Manufacturer Part Number: AM29LV641GH53R
• Description: 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
• Manufacturer: SPANSION [SPANSION]

DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend: L = Logic Low = V
A
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
3. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version
4. D
VersatileI/O™ (V
The VersatileI/O (V
to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
V
V system environment as required.
For example, a V
the 3 volt level, driving and receiving signals to and
from other 3 V devices on the same bus.
13
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
Sector Group Protect (Note 2)
Sector Group Unprotect
(Note 2)
Temporary Sector Group
Unprotect
IN
IO
Protection and Unprotection” section.
ordered.)
= Address In, D
pin. This allows the device to operate in 1.8 V or 3
IN
or D
OUT
Operation
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
I/O
IN
= Data In, D
IO
of 1.65–1.95 volts allows for I/O at
IO
) control allows the host system
) Control
IL
, H = Logic High = V
OUT
V
0.3 V
A D V A N C E
CE#
CC
X
X
L
L
L
L
L
L
= Data Out
±
Table 1. Device Bus Operations
OE#
H
H
X
H
X
H
H
X
L
IH
, V
WE#
H
X
H
X
X
L
L
L
L
ID
= 8.5–12.5 V, V
Am29LV641G
RESET#
I N F O R M A T I O N
V
0.3 V
V
V
V
CC
H
H
H
H
L
ID
ID
ID
±
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
HH
= 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
ACC
V
H
X
X
X
X
X
X
X
HH
IH
.
A1 = H, A0 = L
A1 = H, A0 = L
SA, A6 = H,
Addresses
SA, A6 = L,
(Note 2)
A
A
A
A
X
X
X
IN
IN
IN
IN
IL
. CE# is the power
June 14, 2005
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
DQ15–
High-Z
High-Z
High-Z
D
DQ0
OUT