AM29LV641ML AMD [Advanced Micro Devices], AM29LV641ML Datasheet - Page 11

• Manufacturer Part Number: AM29LV641ML
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend: L = Logic Low = V
A
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
3. If WP# = V
4. D
VersatileIO™ (V
The VersatileIO™ (V
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V
tion” on page 8 for V
For example, a V
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
December 21, 2005
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
Sector Group Protect (Note 2)
Sector Group Unprotect
(Note 2)
Temporary Sector Group
Unprotect
IN
Protection and Unprotection” section.
determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped
from the factory (The SecSi Sector may be factory protected depending on version ordered.)
= Address In, D
IN
or D
Operation
OUT
IL
, the first or last sector remains protected. If WP# = V
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
IN
I/O
= Data In, D
IO
IO
of 1.65–3.6 volts allows for I/O at
IO
) Control
) control allows the host system
options on this device.
IL
, H = Logic High = V
IO
. See “Ordering Informa-
V
0.3 V
CE#
CC
OUT
L
L
L
L
X
L
L
X
±
= Data Out
OE#
H
H
X
H
X
H
H
X
L
Table 1. Device Bus Operations
WE# RESET#
H
H
IH
X
X
X
L
L
L
L
, V
D A T A S H E E T
ID
Am29LV641MH/L
= 11.5–12.5 V, V
V
0.3 V
V
V
V
CC
H
H
H
H
L
ID
ID
ID
±
(Note 3)
(Note 3)
IH
WP#
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
, the first or last sector will be protected or unprotected as
X
X
X
X
H
H
H
HH
= 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
ACC
V
L/H
L/H
L/H
L/H
L/H
L/H
L/H
H
HH
IH
.
A2=L, A1=H, A0=L
A2=L, A1=H, A0=L
SA, A6 =L, A3=L,
SA, A6=H, A3=L,
Addresses
(Note 2)
A
A
A
A
X
X
X
IN
IN
IN
IN
IL
. CE# is the power
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
High-Z
High-Z
High-Z
DQ0–
DQ15
D
OUT
9