ADSP-TS101SAB1Z-100 Analog Devices, ADSP-TS101SAB1Z-100 Datasheet

ADSP-TS101SAB1Z-100

Manufacturer Part Number

ADSP-TS101SAB1Z-100

Description

Manufacturer

Analog Devices

Datasheet

1.ADSP-TS101SAB1Z-000.pdf (44 pages)

Specifications of ADSP-TS101SAB1Z-100

Package

BGA

Date_code

09+

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KEY FEATURES

300 MHz, 3.3 ns instruction cycle rate

6M bits of internal—on-chip—SRAM memory

19 mm × 19 mm (484-ball) or 27 mm × 27 mm

Dual computation blocks—each containing an ALU, a multi-

Dual integer ALUs, providing data addressing and pointer

Integrated I/O includes 14-channel DMA controller, external

1149.1 IEEE compliant JTAG test access port for on-chip

On-chip arbitration for glueless multiprocessing with up to

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

(625-ball) PBGA package

plier, a shifter, and a register file

manipulation

port, four link ports, SDRAM controller, programmable

flag pins, two timers, and timer expired pin for system

integration

emulation

eight TigerSHARC processors on a bus

COMPUTATIONAL BLOCKS

MULTIPLIER

DAB

SHIFTER

32 × 32

128

ALU

FILE

ALU

128

PROGRAM SEQUENCER

IAB

BTB IRQ

FETCH

ADDR

128

I/O PROCESSOR

CONTROLLER

CONTROL/

STATUS/

INTEGER

TCBs

DATA ADDRESS GENERATION

32 × 32

DMA

J ALU

Figure 1. Functional Block Diagram

DMA ADDRESS

DMA DATA

INTEGER

32 × 32

K ALU

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

KEY BENEFITS

Provides high performance Static Superscalar DSP opera-

Performs exceptionally well on DSP algorithm and I/O bench-

Supports low overhead DMA transfers between internal

Eases DSP programming through extremely flexible instruc-

Enables scalable multiprocessing systems with low commu-

tions, optimized for telecommunications infrastructure

and other large, demanding multiprocessor DSP

applications

marks (see benchmarks in

memory, external memory, memory-mapped peripherals,

link ports, other DSPs (multiprocessor), and host

processors

tion set and high level language friendly DSP architecture

nications overhead

MEMORY

64K × 32

256

INTERNAL MEMORY

MEMORY

64K × 32

256

Embedded Processor

I/O ADDRESS

MEMORY

64K × 32

LINK DATA

M0 ADDR

M0 DATA

M1 ADDR

M1 DATA

M2 ADDR

M2 DATA

Table 1

CONTROLLER

LINK PORT

CONTROL/

BUFFERS

STATUS/

ADSP-TS101S

TigerSHARC

SDRAM CONTROLLER

and

MULTIPROCESSOR

HOST INTERFACE

EXTERNAL PORT

OUTPUT BUFFER

OUTPUT FIFO

CLUSTER BUS

INTERFACE

INPUT FIFO

ARBITER

Table

PORTS

JTAG PORT

LINK

www.analog.com

CNTRL

ADDR

DATA

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