N74F373D,602 NXP Semiconductors, N74F373D,602 Datasheet - Page 8

IC DTYPE LATCH OCTAL 20SOIC

N74F373D,602

Manufacturer Part Number
N74F373D,602
Description
IC DTYPE LATCH OCTAL 20SOIC
Manufacturer
NXP Semiconductors
Series
74Fr
Datasheet

Specifications of N74F373D,602

Logic Type
D-Type Transparent Latch
Package / Case
20-SOIC (7.5mm Width)
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
2ns
Current - Output High, Low
3mA, 24mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
F
Polarity
Non-Inverting
High Level Output Current
- 3 mA
Low Level Output Current
32 mA
Propagation Delay Time
5.3 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Current
60 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4640-5
933739560602
N74F373D
N74F373D
Philips Semiconductors
AC WAVEFORMS (continued)
For all waveforms, V
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT AND WAVEFORMS
2002 Nov 20
CP
Dn
SWITCH POSITION
Qn, Qn
OEn
Latch/flip-flop
DEFINITIONS:
R
C
R
t
All other
L =
L =
T =
PLZ
Waveform 6. 3-State output enable time to HIGH level
TEST
GENERATOR
, t
PULSE
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
generators.
Waveform 5. Data set-up time and hold times
PZL
t
V
su
and output disable time from HIGH level
M
V
(H)
M
Test circuit for 3-state outputs
SWITCH
closed
open
t
h
t
V
V
V
PZH
M
(H)
IN
M
M
= 1.5 V.
R
T
D.U.T.
V
V
M
CC
V
t
V
PHZ
OUT
M
t
V
su
M
C
(L)
L
R
R
OUT
t
h
L
V
L
V
(L)
M
M
V
of pulse
OH
SF00263
SF00262
7.0V
-0.3V
0V
NEGATIVE
PULSE
POSITIVE
PULSE
8
family
74F
90%
10%
amplitude
Waveform 7. 3-State output enable time to LOW level
Qn, Qn
OEn
3.0V
V
V
M
90%
M
INPUT PULSE REQUIREMENTS
and output disable time from LOW level
10%
t
t
TLH (
THL (
Input pulse definition
1.5V
V
M
t
t
V
t
PZL
r
f
M
)
)
rep. rate
t
t
w
w
1MHz
V
t
t
TLH (
THL (
M
t
t
r
500ns 2.5ns
f
74F373/74F374
10%
90%
)
)
t
t
w
PLZ
V
V
V
M
M
M
t
TLH
90%
10%
2.5ns
V
t
SF00264
THL
Product data
OL
AMP (V)
0V
0V
SF00265
AMP (V)
+0.3V

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