IDT74ALVCH162373PAG IDT, Integrated Device Technology Inc, IDT74ALVCH162373PAG Datasheet - Page 5

• Manufacturer Part Number: IDT74ALVCH162373PAG
• Description: IC LATCH 16BIT TRANSP D 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74ALVCHr
• Type: D-Typer

Specifications of IDT74ALVCH162373PAG

• Output Type: Tri-State
• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Voltage - Supply: 2.3 V ~ 3.6 V
• Independent Circuits: 2
• Delay Time - Propagation: 1.5ns
• Current - Output High, Low: 12mA, 12mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Logic Family: ALVC
• Number Of Bits: 16
• Number Of Elements: 2
• Latch Mode: Transparent
• Polarity: Non-Inverting
• Technology: CMOS
• Package Type: TSSOP
• Propagation Delay Time: 6.5ns
• Operating Supply Voltage (typ): 3.3V
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH162373PAG; 800-1552; 800-1552-5; 800-1552

TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
SWITCH POSITION
NOTES:
1.
2.
DEFINITIONS:
C
R
Pulse
Generator
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
L
T
Symbol
V
= Termination resistance: should be equal to Z
= Load capacitance: includes jig and probe capacitance.
V
V
For t
For t
LOAD
V
V
C
HZ
LZ
IH
T
OUTPUT 2
L
OUTPUT 1
(1, 2)
SK
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
(o) OUTPUT1 and OUTPUT2 are any two outputs.
All Other Tests
INPUT
Disable High
Disable Low
Enable High
Enable Low
Open Drain
V
CC
Test
(1)
V
= 3.3V±0.3V V
IN
300
300
2.7
1.5
50
6
Test Circuit for All Outputs
t
SK
(x)
Output Skew - t
R
T
D.U.T.
= t
V
t
PLH1
CC
CC
PLH2
t
PLH2
(1)
300
300
2.7
1.5
50
6
= 2.7V
t
V
-
SK
t
OUT
PLH1
(x)
OUT
SK
F
F
(
≤ 2ns; t
X
V
≤ 2.5ns; t
or
of the Pulse Generator.
t
C
)
PHL1
CC
L
t
t
(2)
PHL2
PHL2
2 x Vcc
Switch
Vcc / 2
= 2.5V±0.2V
V
GND
Open
R
Vcc
150
150
LOAD
30
t
500Ω
R
≤ 2ns.
SK
500Ω
ALVC Link
-
≤ 2.5ns.
t
(x)
PHL1
ALVC Link
V
V
0V
V
V
V
V
V
V
Open
GND
IH
T
OH
T
OL
OH
T
OL
V
Unit
mV
mV
pF
LOAD
V
V
V
5
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
ASYNCHRONOUS
SYNCHRONOUS
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORMALLY
CONTROL
HIGH-LOW-HIGH
CONTROL
CONTROL
LOW-HIGH-LOW
OUTPUT
OUTPUT
SAME PHASE
TIMING
INPUT
INPUT
INPUT
HIGH
DATA
LOW
Set-up, Hold, and Release Times
OUTPUT
Enable and Disable Times
PULSE
PULSE
CLOSED
SWITCH
SWITCH
ENABLE
Propagation Delay
OPEN
Pulse Width
t
t
PZL
PZH
INDUSTRIAL TEMPERATURE RANGE
t
t
PLH
PLH
V
t
V
0V
SU
t
SU
T
V
LOAD/2
T
t
W
t
t
PHZ
REM
t
H
t
t
PHL
PHL
t
ABLE
t
H
PLZ
DIS-
ALVC Link
ALVC Link
ALVC Link
V
V
ALVC Link
T
V
V
0V
V
V
V
V
V
0V
T
V
V
0V
V
V
V
V
V
0V
IH
T
LOAD/2
LZ
OL
OH
HZ
IH
T
OH
T
OL
IH
T
V
V
0V
V
V
0V
V
V
0V
V
V
0V
IH
T
IH
T
IH
T
IH
T