74AVC16373DGG,118 NXP Semiconductors, 74AVC16373DGG,118 Datasheet - Page 3

• Manufacturer Part Number: 74AVC16373DGG,118
• Description: IC 16BIT D TRANSP LATCH 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AVCr

Specifications of 74AVC16373DGG,118

• Logic Type: D-Type Transparent Latch
• Package / Case: 48-TSSOP
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 1.2 V ~ 3.6 V
• Independent Circuits: 2
• Delay Time - Propagation: 1.4ns
• Current - Output High, Low: 12mA, 12mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: AVC
• Polarity: Non-Inverting
• Input Bias Current (max): 0.2 uA
• High Level Output Current: - 12 mA
• Low Level Output Current: 8 mA
• Propagation Delay Time: 2.2 ns at 1.65 V to 1.95 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.4 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935265483118

Philips Semiconductors
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
2000 Mar 09
t
C
C
Enable and read register
(transparent mode)
Latch and read register
(hold mode)
Latch register and disable outputs
PHL
I
PD
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
P
f
f
C
V
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high impedance OFF-state.
i
o
/t
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
(C
OPERATING MODES
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
L
PD
V
SYMBOL
amb
CC
V
2
CC
= 25 C; t
f
2
o
) = sum of outputs.
I
f
= GND to V
i
+
r
= t
(C
f
L
2.0 ns.
CC
V
CC
propagation delay
nD
input capacitance
power dissipation
capacitance per buffer
.
nOE
2
n
H
H
L
L
L
L
to nQ
f
o
) where:
PARAMETER
n
INPUTS
LE
H
H
L
L
L
L
3
nA
H
L
h
h
l
l
n
D
in W).
V
V
V
V
V
notes 1 and 2
CC
CC
CC
CC
CC
outputs enabled
outputs disabled
CONDITIONS
INTERNAL
= 1.2 V
= 1.5 V
= 1.8 V
= 2.5 V
= 3.3 V
LATCHES
H
H
H
L
L
L
3.6
3.1
2.2
1.6
1.4
5.0
34
1
TYP.
74AVC16373
Product Specification
OUTPUTS
nY
H
H
Z
Z
L
L
ns
ns
ns
ns
ns
pF
pF
pF
n
UNIT