74ABT841PW,118 NXP Semiconductors, 74ABT841PW,118 Datasheet - Page 4

• Manufacturer Part Number: 74ABT841PW,118
• Description: IC 10BIT BUS INTFC LATCH 24TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ABTr

Specifications of 74ABT841PW,118

• Logic Type: D-Type Transparent Latch
• Circuit: 10:10
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 4ns
• Current - Output High, Low: 32mA, 64mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ABT841PW-T; 74ABT841PW-T; 935178960118

NXP Semiconductors
6. Functional description
Table 3.
[1]
7. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
[2]
74ABT841_3
Product data sheet
Input
OE
L
L
L
L
H
L
Symbol
V
V
V
I
I
I
T
T
IK
OK
O
j
stg
CC
I
O
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
↓ = HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
Function table
Limiting values
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
LE
H
H
↓
↓
X
L
[1]
All information provided in this document is subject to legal disclaimers.
nD
L
H
l
h
X
X
Rev. 03 — 25 March 2010
Conditions
output in OFF-state or HIGH-state
V
V
output in LOW-state
I
O
< 0 V
< 0 V
Output
Q0 to Q9
L
H
L
H
Z
NC
10-bit bus interface latch; 3-state
[1]
[1]
[2]
Min
−0.5
−1.2
−0.5
−18
−50
-
-
−65
Operating mode
transparent
latched
high-impedance
hold
74ABT841
© NXP B.V. 2010. All rights reserved.
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
Unit
V
V
V
mA
mA
mA
°C
°C
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