74ABT841PW,118 NXP Semiconductors, 74ABT841PW,118 Datasheet - Page 6

• Manufacturer Part Number: 74ABT841PW,118
• Description: IC 10BIT BUS INTFC LATCH 24TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ABTr

Specifications of 74ABT841PW,118

• Logic Type: D-Type Transparent Latch
• Circuit: 10:10
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 4ns
• Current - Output High, Low: 32mA, 64mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ABT841PW-T; 74ABT841PW-T; 935178960118

NXP Semiconductors
Table 6.
[1]
[2]
[3]
[4]
10. Dynamic characteristics
Table 7.
GND = 0 V; for test circuit, see
74ABT841_3
Product data sheet
Symbol Parameter
I
ΔI
C
C
Symbol Parameter
t
t
t
t
t
t
t
t
t
t
t
t
CC
PLH
PHL
PZH
PZL
PHZ
PLZ
su(H)
su(L)
h(H)
h(L)
WH
WL
I
O
CC
For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
This parameter is valid for any V
transition time of up to 100 μs is permitted.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input at 3.4 V.
supply current
additional supply current per input pin; V
input capacitance
output capacitance
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
OFF-state to HIGH
propagation delay
OFF-state to LOW
propagation delay
HIGH to OFF-state
propagation delay
LOW to OFF-state
propagation delay
set-up time HIGH
set-up time LOW
hold time HIGH
hold time LOW
pulse width HIGH
pulse width LOW
Static characteristics
Dynamic characteristics
Figure
Conditions
Dn to Qn; see
LE to Qn; see
Dn to Qn; see
LE to Qn; see
OE to Qn; see
OE to Qn; see
OE to Qn; see
OE to Qn; see
Dn to LE; see
Dn to LE; see
Dn to LE; see
Dn to LE; see
LE; see
LE; see
CC
…continued
between 0 V and 2.1 V with a transition time of up to 10 ms. For V
Conditions
V
input at 3.4 V; other inputs at V
or GND
V
outputs disabled; V
9.
CC
I
outputs HIGH-state
outputs LOW-state
outputs disabled
= 0 V or V
Figure 6
Figure 6
= 5.5 V; V
All information provided in this document is subject to legal disclaimers.
Figure 8
Figure 8
Figure 8
Figure 8
Figure 6
Figure 6
Figure 5
Figure 5
Figure 7
Figure 7
Figure 7
Figure 7
CC
Rev. 03 — 25 March 2010
I
CC
= GND or V
= 5.5 V; one
O
= 0 V or V
CC
CC
CC
[4]
25 °C; V
+1.0 −0.8
Min
2.1
2.1
2.0
2.8
1.0
2.2
2.7
2.8
2.5
1.5
1.5
3.3
3.3
Min
-
-
-
-
-
-
Typ
4.1
4.1
4.0
4.6
3.0
4.1
4.7
4.6
1.0
0.2
1.9
1.9
25 °C
10-bit bus interface latch; 3-state
CC
Typ
0
0.5
0.5
0.5
25
4
7
= 5.0 V −40 °C to +70 °C;
Max
5.5
5.9
5.5
6.2
4.5
5.6
6.2
6.1
-
-
-
-
-
-
Max
250
250
1.5
38
CC
-
-
= 2.1 V to V
V
CC
−40 °C to +85 °C Unit
Min
74ABT841
2.1
2.1
2.0
2.8
1.0
2.2
2.7
2.8
2.5
1.5
1.5
1.0
3.3
3.3
Min
= 5.0 V ± 0.5 V
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
CC
= 5 V ± 10 %, a
Max
6.2
6.5
6.2
6.7
5.3
6.3
7.1
6.5
Max
250
250
1.5
38
-
-
-
-
-
-
-
-
6 of 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μA
mA
μA
mA
pF
pF