GS8182D19BGD-400 GSI Technology, GS8182D19BGD-400 Datasheet

GS8182D19BGD-400

Manufacturer Part Number

GS8182D19BGD-400

Description

BGA 165/SYNCHRONOUS SRAM's 1M x 18 (18 Meg) Burst of 4

Manufacturer

GSI Technology

Datasheet

1.GS8182D19BGD-400.pdf (29 pages)

Specifications of GS8182D19BGD-400

Pack_quantity

144

Comm_code

85423245

Lead_time

Current page: 1 of 29
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165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD)

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad™ Family Overview

The GS8182D19/37D are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 18,874,368-bit (18Mb)

SRAMs. The GS8182D19/37D SigmaQuad SRAMs are just

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Rev: 1.00a 6/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tKHKH

tKHQV

0.45 ns

2.5ns

-400

Parameter Synopsis

1/29

18Mb SigmaQuad-II+

Burst of 4 SRAM

2.67 ns

0.45 ns

-375

Clocking and Addressing Schemes

The GS8182D19/37D SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Separate I/O SigmaQuad-II+ Burst of 4 RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

incremented by 1 for the next transfers.

1 mm Bump Pitch, 11 x 15 Bump Array

0.45 ns

3.3 ns

165-Bump, 13 mm x 15 mm BGA

-333

GS8182D19/37BD-400/375/333/300

Bottom View

0.45 ns

3.0 ns

-300

1.8 V and 1.5 V I/O

400 MHz–300 MHz

Preliminary

1.8 V V

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