GS832136GE-166 GSI Technology, GS832136GE-166 Datasheet

GS832136GE-166

Manufacturer Part Number

GS832136GE-166

Description

bga 165/SYNCHRONOUS SRAM's 1M x 36 (36 Meg) Synch Burst

Manufacturer

GSI Technology

Datasheet

1.GS832118E-166I.pdf (32 pages)

Specifications of GS832136GE-166

Pack_quantity

105

Comm_code

85423245

Lead_time

Current page: 1 of 32
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165-Bump FP-BGA

Commercial Temp

Industrial Temp

Features

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 165-bump FP-BGA package

• RoHS-compliant 165-bump BGA package available

Functional Description

Applications

The GS832118/32/36E is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx,

BW, GW) are synchronous and are controlled by a positive-

edge-triggered clock input (CK). Output enable (G) and power

down control (ZZ) are asynchronous inputs. Burst cycles can

be initiated with either ADSP or ADSC inputs. In Burst mode,

subsequent burst addresses are generated internally and are

controlled by ADV. The burst address counter may be

configured to count in either linear or interleave order with the

Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Rev: 1.05 12/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

Curr

tCycle

(x32/x36)

(x18)

Parameter Synopsis

1/32

-250 -225 -200 -166 -150 -133 Unit

285

350

205

235

2.5

4.0

6.5

265

320

195

225

2.7

4.4

7.0

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD Pipelined Reads

The GS832118/32/36E is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS832118/32/36E operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

245

295

185

210

3.0

5.0

7.5

GS832118/32/36E-250/225/200/166/150/133

220

260

175

200

3.5

6.0

8.0

210

240

165

190

3.8

6.6

8.5

DDQ

185

215

155

175

4.0

7.5

8.5

) pins are used to decouple output noise

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

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