GS8321E36AGD-150IV GSI Technology, GS8321E36AGD-150IV Datasheet

GS8321E36AGD-150IV

Manufacturer Part Number

GS8321E36AGD-150IV

Description

PBGA 165/CACHE SRAM

Manufacturer

GSI Technology

Datasheet

1.GS8321E36AGD-333V.pdf (30 pages)

Specifications of GS8321E36AGD-150IV

Pack_quantity

Comm_code

85423245

Lead_time

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165-Bump BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Dual Cycle Deselect (DCD) operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 165-bump BGA package

• RoHS-compliant 165-bump BGA package available

Functional Description

Applications

The GS8321E18/32/36AD-xxxV is a 37,748,736-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK3). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be

initiated with either ADSP or ADSC inputs. In Burst mode,

subsequent burst addresses are generated internally and are

controlled by ADV. The burst address counter may be

configured to count in either linear or interleave order with the

Rev: 1.00a 2/2011

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

Curr

tCycle

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

(x32/x36)

(x18)

Parameter Synopsis

1/30

-333

290

335

210

240

3.0

5.0

Linear Burst Order (LBO) input. The Burst function need not be

used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode pin (Pin 14). Holding the FT mode pin low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipeline mode, activating the rising-edge-triggered Data

Output Register.

DCD Pipelined Reads

The GS8321E18/32/36AD-xxxV is a DCD (Dual Cycle

Deselect) pipelined synchronous SRAM. SCD (Single Cycle

Deselect) versions are also available. DCD SRAMs pipeline

disable commands to the same degree as read commands. DCD

RAMs hold the deselect command for one full cycle and then

begin turning off their outputs just after the second rising edge of

clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS8321E18/32/36AD-xxxV operates on a 1.8 V or 2.5 V

power supply. All inputs are 1.8 V or 2.5 V compatible. Separate

output power (V

from the internal circuits and are 1.8 V or 2.5 Vcompatible.

-250

230

270

180

210

3.0

4.0

5.5

-200

190

225

160

185

3.0

5.0

6.5

DDQ

) pins are used to decouple output noise

-150

155

180

140

160

3.8

6.7

7.5

GS8321E18/32/36AD-xxxV

Unit

333 MHz–150 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Preliminary

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