GS8322Z18B-225I GSI Technology, GS8322Z18B-225I Datasheet

GS8322Z18B-225I

Manufacturer Part Number

GS8322Z18B-225I

Description

BGA 119

Manufacturer

GSI Technology

Datasheet

1.GS8322Z36E-166I.pdf (40 pages)

Specifications of GS8322Z18B-225I

Pack_quantity

Comm_code

85423245

Lead_time

Current page: 1 of 40
Download datasheet (2Mb)

119, 165 & 209 BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165- or 209-Bump BGA package

• Pb-Free packages available

Functional Description

The GS8322Z18/36/72 is a 36Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.07 4/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Through

Pipeline

3-1-1-1

2-1-1-1

36Mb Pipelined and Flow Through

Flow

Synchronous NBT SRAM

KQ (x18/x36)

Curr

tCycle

KQ (x72)

(x18)

(x36)

(x72)

(x18)

(x36)

(x72)

Parameter Synopsis

1/40

-250 -225 -200 -166 -150 -133 Unit

285

350

440

205

235

315

2.5

3.0

4.0

6.5

265

320

410

195

225

295

2.7

3.0

4.4

7.0

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8322Z18/36/72 may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8322Z18/36/72 is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump, 165-bump or 209-bump BGA package.

245

295

370

185

210

265

3.0

5.0

7.5

220

260

320

175

200

255

3.5

6.0

8.0

210

240

300

165

190

240

3.8

6.7

8.5

185

215

265

155

175

230

4.0

7.5

8.5

250 MHz–133 MHz 2.5

2.5 V or 3.3 V I/O

V or 3.3 V V

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