GS84032AB-100 GSI Technology, GS84032AB-100 Datasheet

GS84032AB-100

Manufacturer Part Number

GS84032AB-100

Description

Manufacturer

GSI Technology

Datasheet

1.GS84018AGT-100I.pdf (31 pages)

Specifications of GS84032AB-100

Pack_quantity

Comm_code

85423245

Lead_time

Current page: 1 of 31
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TQFP, BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or 119-bump BGA

• RoHS-compliant 100-lead TQFP and 119-bump BGA

Functional Description

Applications

The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications ranging from DSP main store

to networking chip set support. The GS84018/32/36A is

available in a JEDEC standard 100-lead TQFP or 119-Bump

BGA package.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Rev: 1.19 10/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

packages

packages available

, E

256K x 18, 128K x 32, 128K x 36

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

, E

4Mb Sync Burst SRAMs

), address burst

tCycle

Parameter Synopsis

1/31

335 mA

210 mA

5.5 ns

3.0 ns

–180

8 ns

9 ns

310 mA

190 mA

6.0 ns

3.5 ns

8.5 ns

10 ns

–166

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin/bump (pin 14 in the TQFP and

bump 5R in the BGA). Holding the FT mode pin/bump low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipelined mode, activating the rising-edge-triggered

Data Output Register.

SCD Pipelined Reads

The GS84018/32/36A is an SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using byte write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS84018/32/36A operates on a 3.3 V power supply and

all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

280 mA

165 mA

6.6 ns

3.8 ns

10 ns

12 ns

–150

GS84018/32/36AT/B-180/166/150/100

DDQ

190 mA

135 mA

4.5 ns

10 ns

12 ns

15 ns

–100

) pins are used to de-couple output noise

180 MHz–100 MHz

3.3 V and 2.5 V I/O

3.3 V V

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