GS8662T20BGD-400 GSI Technology, GS8662T20BGD-400 Datasheet

GS8662T20BGD-400

Manufacturer Part Number

GS8662T20BGD-400

Description

Manufacturer

GSI Technology

Datasheet

1.GS8662T20BGD-400.pdf (33 pages)

Specifications of GS8662T20BGD-400

Pack_quantity

105

Comm_code

85423245

Lead_time

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165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.5 Clock Latency

• Simultaneous Read and Write SigmaDDR

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaDDR-II™ Family Overview

The GS8662T06/11/20/38BD are built in compliance with the

SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

Rev: 1.00 5/2010

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

and Clock (K, K) inputs

tKHKH

tKHQV

tKHKH

tKHQV

1.81 ns

0.29ns

0.37ns

2.2 ns

Interface

72Mb SigmaDDR

-550

-450

Parameter Synopsis (x18/x36)

Parameter Synopsis (x8/x9)

Burst of 2 SRAM

1/33

0.33 ns

0.45 ns

2.0 ns

2.5 ns

-500

-400

SRAMs. The GS8662T06/11/20/38BD SigmaDDR-II+

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

The GS8662T06/11/20/38BD SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Common I/O SigmaDDR-II+ RAMs always transfer

data in two packets, A0 is internally set to 0 for the first read

or write transfer, and automatically incremented by 1 for the

next transfer. Because the LSB is tied off internally, the

address field of a SigmaDDR-II+ B2 RAM is always one

address pin less than the advertised index depth (e.g., the 4M x

18 has a 2M addressable index).

Clocking and Addressing Schemes

0.37 ns

2.66 ns

0.45 ns

2.2 ns

-450

-375

-II+

GS8662T20/38BD-550/500/450/400

GS8662T06/11BD-450/400/375/333

0.45 ns

2.5 ns

3.0 ns

-400

-333

550 MHz–333 MHz

1.8 V or 1.5 V I/O

Preliminary

1.8 V V

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