AM29LVI16D AMD [Advanced Micro Devices], AM29LVI16D Datasheet - Page 15

• Manufacturer Part Number: AM29LVI16D
• Description: 16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-indepen-
dent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families.
Flash vendors can standardize their existing interfaces
for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array
14
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
Figure 2. Temporary Sector Unprotect Operation
again.
Unprotect Completed
Program Operations
Temporary Sector
Perform Erase or
RESET# = V
RESET# = V
(Note 1)
(Note 2)
START
ID
IH
Am29LV116D
against inadvertent writes (refer to Table 9 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
data. The system can read CFI information at the
addresses given in Tables 5–8. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represen-
tative for copies of these documents.
IL
, CE# = V
CC
CC
Write Inhibit
is less than V
IH
or WE# = V
IL
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
IH
, the device does not ac-
. To initiate a write cycle,
IH
during power up, the
CC
LKO
power-up and
.
CC
CC