AM29PDL640G AMD [Advanced Micro Devices], AM29PDL640G Datasheet - Page 13

• Manufacturer Part Number: AM29PDL640G
• Description: 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend: L = Logic Low = V
A
Notes:
1. Addresses are A21–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC
specifications and to Figure 12 for the timing diagram.
I
tive current specification for reading array data.
December 13, 2005
CC1
Read
Write
Standby
Output Disable
Reset
Temporary Sector Unprotect (High
Voltage)
IN
Sector Protection
= Address In, D
in the DC Characteristics table represents the ac-
Operation
Read-Only Operations
IN
section.
IH
= Data In, D
.
IL
, H = Logic High = V
OUT
Table 1. Am29PDL640G Device Bus Operations
IL
= Data Out
0.3 V
CE#
V
. CE# is the power
IO
X
X
L
L
L
±
table for timing
OE#
IH
D A T A S H E E T
H
X
H
X
L
X
, V
ID
Am29PDL640G
= 11.5–12.5 V, V
WE#
H
X
H
X
X
L
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Random Read (Non-Page Read)
Address access time (t
stable addresses to valid output data. The chip enable
access time (t
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
inputs (assuming the addresses have been stable for
at least t
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 8 words, with the appropriate page being
selected by the higher address bits A21–A3 and the
LSB bits A2–A0 determining the specific word within
that page. This is an asynchronous operation with the
microprocessor supplying the specific word location.
The random or initial page access is equal to t
t
the locations specified by the microprocessor falls
within that page) is equivalent to t
CE
RESET#
V
0.3 V
V
and subsequent page read accesses (as long as
IO
H
H
H
L
ID
HH
±
= 8.5–9.5 V, X = Don’t Care, SA = Sector Address,
ACC
–t
OE
WP#/ACC
CE
time).
) is the delay from the stable ad-
X
X
X
X
X
X
ACC
) is equal to the delay from
Addresses
(Note 1)
A
A
A
X
X
X
PACC
IN
IN
IN
. When CE# is
High Voltage
DQ15–
High-Z
High-Z
High-Z
D
DQ0
D
D
OUT
ACC
IN
IN
11
or