AK4687 AKM [Asahi Kasei Microsystems], AK4687 Datasheet
AK4687
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AK4687 Summary of contents
Page 1
... Asynchronous Stereo CODEC with Capless Stereo Selector The AK4687 is a stereo audio CODEC with 2-channel input selector and a line driver. The interfaces of ADC/DAC can accept up to 24bit input data and support asynchronous operation. The input range of the pre-amplifier, that supports 3ch stereo inputs, is selectable by external resistors. Both the input stereo selector and output drivers support ground reference 2Vrms In/Output, making it possible to remove AC-coupling capacitors and reducing external parts ...
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... LOUT ROUT AVDD1 VSS1 AVDD2 VSS2 MS1307-E-00 PWAD bit PDN1 pin 2ch HPF ADC PWDA bit PDN2 pin De-em 2ch DAC VREF1 DVDD VSS3 VSS4 VSS5 AK4687 Block Diagram - 2 - [AK4687] PORT1 PDN1 MCLK1 BICK1 Serial LRCK1 I/F SDTO MSN I2C Control SDA/AIN1 I/F SCL/AIN0 ...
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... Ordering Guide -20 ∼ +85°C AK4687EQ AKD4687 Evaluation Board for the AK4687 ■ Pin Layout 37 RIN3 LIN3 RIN2 40 LIN2 RIN1 43 LIN1 I2C 46 SDA/AIN1 47 SCL/AIN0 48 MS1307-E-00 48pin LQFP (0.5mm pitch) AK4687EQ Top View - 3 - [AK4687] 24 LOUT 23 ROUT CVEE 20 CN ...
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... This pin must be connected to the ground 40 RIN2 I Rch Input 2 Pin 41 LIN2 I Lch Input 2 Pin This pin must be connected to the ground 43 RIN1 I Rch Input 1 Pin 44 LIN1 I Lch Input 1 Pin This pin must be connected to the ground MS1307-E-00 PIN/FUNCTION Function - 4 - [AK4687] 2011/05 ...
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... PIN/FUNCTION (Continued) Function 2 C control, “L”= H/W control ABSOLUTE MAXIMUM RATINGS Note 1) Symbol DVDD AVDD1 AVDD2 IIN VIND ) pins VINA Ta Tstg Note 1) Symbol min DVDD 3.0 AVDD1 3.0 AVDD2 3 [AK4687] min max Units -0.3 4.0 V -0.3 4.0 V -0.3 4 ±10 mA -0.3 DVDD+0.3 V -0.3 AVDD1+0.3 V °C -20 85 °C -65 150 typ max Units 3 ...
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... Units kΩ kΩ Vrms kΩ pF Bits ppm/°C dB Bits ppm/°C Vrms kΩ 2011/05 ...
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... AK4687 0V MS1307-E-00 LOUT/ROUT 470 C1 2.2nF Figure 1. Lineout Circuit Example LIN1 R i LIN2 - + R i LIN3 0V AK4687 Figure 2. External Circuit of Pre-Amp - 7 - [AK4687] Analog Out C L ADC 2011/05 ...
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... FILTER CHARACTERISTICS Symbol min ±0.1dB -0.2dB - -3.0dB SB 28 ΔGD -3dB FR -0.1dB 26 fs=44.1kHz FR - fs=96kHz FR - fs=192kHz [AK4687] typ max Units μ typ max Units 18.8 kHz 21.1 - kHz 21.7 - kHz kHz dB 17 1/fs 0 µs 1.0 Hz 7.1 Hz 21.7 kHz 24 ...
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... Units μA Units MHz % MHz 1/fCLK 1/fCLK MHz 1/fCLK 1/fCLK MHz 1/fCLK 1/fCLK MHz 1/fCLK 1/fCLK kHz % kHz kHz kHz % kHz ...
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... [AK4687] min typ max Units 324 ns 128 ns 128 ...
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... SDTI MS1307-E-00 1/fCLK tCLKH tCLKL 1/fsn, 1/fsd, 1/fsq tBCK tBCKH tBCKL Clock Timing (Normal mode) tLRB tLRS tSDS tSDH Audio Interface Timing - 11 - [AK4687] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tBSD 50% TVDD VIH VIL LRCK= LRCK1, LRCK2 BICK= BICK1, BICK2 ...
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... Stop Start MS1307-E-00 tMBLR Audio Interface timing (Master Mode) tPD tPDV Power Down & Reset Timing tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start Bus mode Timing - 12 - [AK4687] 50% DVDD 50% DVDD tBSD 50% DVDD VIH VIL 50% DVDD VIH VIL tSP VIH VIL tSU:STO Stop 2011/05 ...
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... MCLK1 (MCLK2), LRCK1 (LRCK2) and BICK1 (BICK2) are input in slave mode (MSN pin = “L”). When the reset is released (PDN1/2 pin = “L” → “H”), such as after power up the device, the ADC/DAC of AK4687 is in power down state until MCLK1/2, LRCK1/2 and BICK1/2 is input. ...
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... LRCK1 but the phase is not critical. After exiting reset following power-up (PDN1 pin = “L” → “H”), the ADC of AK4687 is in power down state until MCLK1, LRCK1 and BICK1 are input. The ADC only supports Normal Speed Mode (fs = 32k ~ 48kHz). ...
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... MCLK2 (MHz) 128fs 192fs 256fs 22.5792 33.8688 - 24.5760 36.8640 - - 15 - (default) 32kHz~48kHz 64kHz~96kHz 128kHz~192kHz - BICK2 (MHz) 768fs 64fs 24.5760 2.0480 33.8688 2.8224 36.8640 3.0720 BICK2 (MHz) 384fs 64fs 33.8688 5.6448 36.8640 6.1440 BICK2 (MHz) 384fs 64fs - 11.2896 - 12.2880 [AK4687] (Table 9). 2011/05 ...
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... De-emphasis Filter The DAC of AK4687 includes a digital de-emphasis filter (tc=50/15μs) by IIR filter. Setting the DEM1 bit to “1” enables the de-emphasis filter. Refer to “FILTER CHARACTERISTICS” about the gain error when this filter is ON. The de-emphasis filter is OFF in double speed mode (MCLK2= 256fs/38fs ) and quad speed mode (MCLK2=128fs/192fs). ...
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... Left justified H/L 2 24bit L/H Table 18. Audio Interface Format (DAC 17). BICK1 speed I/O ≥ 48fs (default) 32fs ≥ 48fs I I 64fs O (default) 64fs O BICK2 I/O speed I/O ≥ 32fs I I ≥ 48fs I I ≥ 48fs I I (default) ≥ 48fs I I [AK4687] 2011/05 ...
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... Rch Data Don’t Care Rch Data Don’t Care Rch Data [AK4687 2011/05 ...
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... Input Selector The AK4687 has 3:1 stereo input selectors. AIN1-0 bits control each input channel in I control each selector in H/W control mode. AIN1 bit Table 19. ADC Input Selector (I AIN1 pin Table 20. ADC Input Selector (H/W Control Mode) ■ Pre-Amp and Input ATT ...
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... H AK4687 Charge Pump CP CN VSS3 Cb (+) Ca (+) 1uF Figure 8. Charge Pump Circuit - 20 - MCLK2, BICK2, LRCK2 CP status x active (×: Don’t Care Control Mode) MCLK2, BICK2, LRCK2 CP status x ON active ON (×: Don’t Care) Negative Power VEE 1uF [AK4687 2011/05 ...
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... System Reset When power-up the AK4687, the PDN1 and PDN2 pins should be “L” and changed to “H” after all power supplies (DVDD, AVDD1, and AVDD2) are supplied. After this reset is released (PDN1 and PDN2 pins = “L” → “H”), all blocks are in power-down mode. This ensures that all internal registers reset to their initial values. ADC internal circuit, control registers for ADC (Addr: 01h-02h) and PWAD bit are reset by PDN1 pin = “ ...
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... Power ON/OFF Sequence The ADC and DAC blocks of the AK4687 are placed in power-down mode by bringing the PDN1 pin and PDN2 pin to “L” respectively and both digital filters are reset at the same time. The PDN1 pin = PDN2 pin =“L” also reset the control registers to their default values. In power-down mode, the DAC outputs 0V and the SDTO pin goes to “ ...
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... The PDN1 and PDN2 pins should be changed from “L” to “H” after power up. “L” time of 150ns or more is needed to reset the AK4687. The PDN pins must be held to “L” until all power supply pins are fed. After all powers are risen up, the PDN1 and PDN2 pins should be set to “H”. ...
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... Serial Control Interface 2 The AK4687 supports fast-mode I C-bus system (max: 400kHz). 1. Data Transfer In order to access any IC devices on the I includes the device address. IC devices on the BUS compare this slave address with their own addresses and the IC device which has an identical address with the slave-address generates an acknowledgement. The IC device with the identical address executes either a read or a write operation ...
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... An external device that is sending data to the AK4687 releases the SDA line (“H”) after receiving one-byte of data. An external device that receives data from the AK4687 then sets the SDA line to “L” at the next clock. This operation is called “acknowledgement”, and it enables verification that the data transfer has been properly executed. The AK4687 generates an acknowledgement upon receipt of a start condition and Slave address ...
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... The AK4687 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4687 generates an acknowledge, and awaits the next data again. The master can transmit more than one data word instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 03H prior to generating a stop condition, the address counter will “ ...
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... After receipt of the slave address with R/W bit set to “1”, the AK4687 generates an acknowledge, transmits 1byte data, which address is set by the internal address counter, and increments the internal address counter the master does ...
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... DAC is powered down by setting the PWDA bit to “0”. However, registers for DAC (Addr: 03h) is not initialized. The bits defined as 0 must contain a “0” value. MS1307-E- DIF1 0 ACKS DFS1 DFS0 - 28 - [AK4687 PWDA PWAD 0 0 AIN1 AIN0 0 CKS1 CKS0 DEM DIF21 DIF20 SMUTE 0 2011/05 ...
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... LIN1/RIN1 (default) 01: LIN2/RIN2 10: LIN3/RIN3 11: Reserved MS1307-E- (Table 19 [AK4687 PWDA PWAD RD RD R/W R AIN1 AIN0 RD RD R/W R 2011/05 ...
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... When ACKS bit = “0”, DFS1-0 bits select the sampling speed mode, and the MCLK frequency is automatically detected in each mode. MS1307-E- DIF1 R ACKS DFS1 DFS0 RD R/W R/W R [AK4687 CKS1 CKS0 RD R/W R DEM DIF21 DIF20 SMUTE R/W R/W R/W R 2011/05 ...
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... PDN2 8 MCLK2 9 BICK 10 LRCK 11 SDTI 12 CAD0 0.1u ∗ 10u ∗ 3. Control mode, CAD0 pin = “L”, Master mode 39k 39k RI 33 ∗ VREF1 AVDD1 31 + 10u 0.1u VSS1 30 VSS4 29 VSS5 28 ∗ 27 VSS2 0.1u 10u AVDD2 26 VREF2 25 Analog Out [AK4687] 3.3V 3.3V 2011/05 ...
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... MSN 2 SDTO 3 LRCK1 BICK1 4 5 MCLK1 AK4687EQ 6 PDN1 7 PDN2 8 MCLK2 9 BICK 10 LRCK 11 SDTI 12 CKS 0.1u ∗ 10u ∗ 3. 39k 39k RI 33 ∗ VREF1 AVDD1 31 + 0.1u 10u VSS1 30 VSS4 29 VSS5 28 ∗ VSS2 27 0.1u 10u AVDD2 26 VREF2 25 Analog Out [AK4687] 3.3V 3.3V 2011/05 ...
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... ADC (LO and RO pins). The ADC output data format is 2’s complement. The internal digital HPF removes the DC offset. The AK4687 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4687 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs ...
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... Material & Lead Finish Package molding compound: Epoxy, Halogen (Br and Cl) free Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate MS1307-E-00 PACKAGE 9.0 ± 0.2 7 0.22 ± 0.08 0.10 M 0° ∼ 10° 0.3 ∼ 0.75 0. [AK4687] 1.70Max 0.13 ± 0.13 1.40 ± 0.05 0.09 ∼ 0.20 2011/05 ...
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... Date (YY/MM/DD) Revision 11/05/30 00 MS1307-E-00 MARKING AK4687EQ XXXXXXX 1 1) Pin #1 indication 2) Marking Code: AK4687EQ 3) Date Code: XXXXXXX (7 digits) REVISION HISTORY Reason Page Contents First Edition - 35 - [AK4687] 2011/05 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1307-E-00 IMPORTANT NOTICE , and AKM assumes no responsibility for such use, except for the use Note2 [AK4687] in any safety, life support, or Note1) 2011/05 ...