AK4687 AKM [Asahi Kasei Microsystems], AK4687 Datasheet - Page 21

• Manufacturer Part Number: AK4687
• Description: Asynchronous Stereo CODEC with Capless Stereo Selector
• Manufacturer: AKM [Asahi Kasei Microsystems]

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Power supply voltage for analog input/output is applied from a regulator for positive power and a charge-pump for
negative power. The analog output is single-ended and centered on 0V (VSS2). Therefore, a capacitor for AC-coupling
can be removed. The minimum load resistance is 5kΩ. When the DAC input signal level is 0dBFS, the output voltage is
2Vrms.
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The DAC has a soft mute function. The soft mute operation is performed at digital domain. When the SMUTE bit goes to
“1”, the input data is attenuated by -∞ in 1024LRCK cycle. When the SMUTE bit returns to “0”, the mute is cancelled and
the attenuation level gradually changes to 0dB in 1024 LRCK cycle. If the soft mute is cancelled before attenuating to -∞
after starting the operation, the attenuation is discontinued and the attenuation level returns to 0dB in the same cycle. The
soft mute is effective for changing the signal source without stopping the signal transmission.
Notes:
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When power-up the AK4687, the PDN1 and PDN2 pins should be “L” and changed to “H” after all power supplies
(DVDD, AVDD1, and AVDD2) are supplied. After this reset is released (PDN1 and PDN2 pins = “L” → “H”), all blocks
are in power-down mode. This ensures that all internal registers reset to their initial values. ADC internal circuit, control
registers for ADC (Addr: 01h-02h) and PWAD bit are reset by PDN1 pin = “L”. DAC internal circuit, control registers for
DAC (Addr: 03h) and PWDA bit are reset by PDN2 pin = “L”. When both PDN1 and PDN2 pins are “L”, all blocks,
resisters and charge pump are powered-down. In H/W control mode, register settings are ignored and the power-down
controls by PDN1 and PDN2 pins are available.
MS1307-E-00
(1) In normal speed mode, the input data is attenuated to -∞ in 1024LRCK cycle. For example, this time is 2048LRCK
(2) The analog output corresponding to the digital input has group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
Analog Input/Output (LIN1-3/RIN1-3, LOUT/ROUT pins)
Soft Mute
System Reset
SMUTE bit
Attenuation
LOUT/ROUT
cycles (2048/fs) in Double Speed Mode, and 4096LRCK cycle (4096/fs) in Quad Speed Mode.
the attenuation level returns to 0dB in the same cycle.
0dB
-∞
1024/fs
(1)
Figure 9. Soft Mute Function
GD
- 21 -
(2)
1024/fs
GD
(3)
[AK4687]
2011/05