AK4687 AKM [Asahi Kasei Microsystems], AK4687 Datasheet - Page 26

• Manufacturer Part Number: AK4687
• Description: Asynchronous Stereo CODEC with Capless Stereo Selector
• Manufacturer: AKM [Asahi Kasei Microsystems]

2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4687.
After receipt of the start condition and the first byte, the AK4687 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4687. The format is MSB first, and
those most significant 3-bits are “Don’t care”.
After receipt of the second byte, the AK4687 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
The AK4687 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4687 generates an acknowledge, and awaits the next data again. The master can
transmit more than one data word instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceeds 03H prior to generating a stop condition, the address counter will “roll over” to 00H
and the previous data will be overwritten.
MS1307-E-00
SDA
D7
*
S
T
A
R
T
S
Slave
Address
D6
*
Figure 16. Byte Structure after the Second Byte
A
C
K
D5
*
Register
Address(n)
Figure 17. WRITE Operation
Figure 15. The Second Byte
A4
D4
A
C
K
- 26 -
Data(n)
A3
D3
A
C
K
Data(n+1)
A2
D2
A
C
K
A1
D1
(*: Don’t care)
Data(n+x)
A0
D0
S
T
O
P
P
[AK4687]
2011/05