HY57V281620FLTP Hynix Semiconductor, HY57V281620FLTP Datasheet - Page 4

• Manufacturer Part Number: HY57V281620FLTP
• Description: Synchronous DRAM Memory 128Mbit (8Mx16bit)
• Manufacturer: Hynix Semiconductor

Rev. 1.2 / Oct. 2007
PIN DESCRIPTION
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDDQ/VSSQ
SYMBOL
A0 ~ A11
BA0, BA1
VDD/VSS
CLK
CKE
NC
CS
Data Output Power/Ground Power supply for output buffers
Data Input/Output Mask
Column Address Strobe,
Power Supply/Ground
Row Address Strobe,
Data Input/Output
No Connection
Bank Address
Clock Enable
Write Enable
Chip Select
Address
TYPE
Clock
The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
No connection
DESCRIPTION
HY57V281620F(L/S)TP Series
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