MT90528AG ZARLINK [Zarlink Semiconductor Inc], MT90528AG Datasheet

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MT90528AG

Manufacturer Part Number

MT90528AG

Description

28-Port Primary Rate Circuit Emulation AAL1 SAR

Manufacturer

ZARLINK [Zarlink Semiconductor Inc]

Datasheet

1.MT90528AG.pdf (195 pages)

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Features

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UTOPIA

Interface

AAL1 Segmentation and Reassembly device

compliant with Circuit Emulation Services (CES)

standard (af-vtoa-0078.000)

Supports both Unstructured and Structured

Circuit Emulation of 28 independent DS1/E1/ST-

BUS interfaces

Supports AAL1 trunking, with up to 128 TDM

channels per VC (af-vtoa-0089.001)

Supports CAS transmission and reception in all

structured modes of operation

Supports simultaneous processing of up to 896

bidirectional Virtual Circuits

Supports mixed DS1/E1 operation

Supports mixed Unstructured and Structured

CES operation

Fully flexible DS0 assignment

Complete clock recovery solution provided on-

chip: Synchronous, Adaptive, or Synchronous

Residual Time Stamp (SRTS) via 28 independent

PLLs

MT90528

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

OUTPUT

UTOPIA

UTOPIA

BLOCK

BLOCK

INPUT

Copyright 2002-2006, Zarlink Semiconductor Inc. All Rights Reserved.

Scan Logic

Boundary-

Interface

JTAG

(UDT, SDT,

RX SARs

Figure 1 - MT90528 Block Diagram

SAR

TX

Data)

VC Look-Up

Table

Zarlink Semiconductor Inc.

External Memory Controller

1

Segmentation / Reassembly

Memory

Memory

Local

Local

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Circular Buffers

16-bit Microprocessor

Dual-mode (ATM-end or PHY-end) UTOPIA port

operates in Level 1 or Level 2 mode for

connection to external PHY or ATM devices with

UTOPIA clock rate up to 52 MHz

TDM bus provides 28 bidirectional serial streams

at 1.544, 2.048, or 4.096 MHz - compatible with

Generic (1.544 Mbps or 2.048 Mbps) and ST-

BUS (2.048 Mbps) interfaces

Supports master and slave TDM backplane bus

clock operation

Supports TDM and UTOPIA loopback functions

16-bit microprocessor port, configurable to

Motorola or Intel timing

Master clock rate of 66.0 MHz

MT90528AG

MT90528AG2

Microprocessor

Interface Logic

Rx/Reassembly (X 28)

Tx/Segmentation (X 28)

Interface

Circuit Emulation AAL1 SAR

PLL

**Pb Free Tin/Silver/Copper

Ordering Information

Management

OUTPUT

BLOCK

Clock

BLOCK

INPUT

TDM

-40 to +85°C

External

Synchronous

SRAM (ZBT)

TDM

28-Port Primary Rate

456 PBGA

456 PBGA**

MT90528

Data Sheet

Clock Control

/Recovery

Interface

TDM Output

Interface

TDM Input

Interface

Trays

Trays

August 2006

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