MT90528AG ZARLINK [Zarlink Semiconductor Inc], MT90528AG Datasheet - Page 75

• Manufacturer Part Number: MT90528AG
• Description: 28-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

sync
invalid
out_of_seq
Current State
Table 15 - Operation of UDT Fast Sequence Number Processing State Machine
late cell timeout period reached and
CHECK_LATE_ARRIVALS = ‘1’
invalid sequence number
received cell is in sequence with previous cell
received cell is not in sequence with the
previously-received cell -> received cell has a
sequence number one greater than the
expected sequence number
received cell is not in sequence with the
previously-received cell -> received cell has a
sequence number that is NOT one greater
than the expected sequence number
invalid sequence number
received cell is in sequence with last “good”
cell (i.e., cell misinsertion)
received cell has a valid sequence number
that is two greater than the last “good” cell
(i.e., sequence number protection failure)
received cell has valid sequence number, but
doesn’t meet either of the 2 previous criteria
invalid sequence number
received cell is in sequence with last received
cell (i.e., multiple cell loss)
received cell has a valid sequence number
that is two greater than the last in-sequence
cell (i.e., sequence number protection failure)
received cell has valid sequence number, but
doesn’t meet either of the 2 previous criteria
Transition Event
Zarlink Semiconductor Inc.
MT90528
75
- UDT RX_SAR inserts a single
dummy cell
- accept received cell
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- assume single-cell loss event
- UDT RX_SAR inserts a single
dummy cell
- after dummy cell insertion, accept
received cell (in-order dummy cell
insertion)
- declare aal1_seq_error
- cannot assume what happened
(may be a multi-cell loss case)
- accept received cell (thus, if this is
a multi-cell loss case, out-of-order
dummy cell insertion will occur)
- declare aal1_seq_error
- discard cell
- discard cell
- declare misinserted_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- discard cell
- discard cell
- calculate number of lost cells (up
to 7)
- UDT RX_SAR inserts dummy
cell(s)
- after dummy cell insertion(s),
accept received cell
- declare lost_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- discard cell
Action Taken
late_cell_insertion
invalid
sync
single_cell_loss_
misinsertion
out_of_seq
start
sync
sync
out_of_sync
start
sync
sync
out_of_sync
Next State
Data Sheet
Note
**
**
**
**
**