MT90528AG ZARLINK [Zarlink Semiconductor Inc], MT90528AG Datasheet - Page 27

• Manufacturer Part Number: MT90528AG
• Description: 28-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

G5, H22, L5, M22, R5, T22, W5,
M14, M15, M16, N11, N12, N13,
AB21, E6, E10, E14, E18, E21,
L14, L15, L16, M11, M12, M13,
N14, N15, N16, P11, P12, P13,
P14, P15, P16, R11, R12, R13,
F5, F22, J5, K22, N5, P22, U5,
R14, R15, R16, T11, T12, T13,
AB5, AB7, AB11, AB15, AB19,
AA5, AB6, AB9, AB13, AB17,
E8, E12, E13, E16, E20, E22,
B12, D13, E5, L11, L12, L13,
T14, T15, T16
AB22, AE3
Ball Pin #
C13
C20
D19
A12
B20
A21
E19
V22
Y22
Table 6 - Master Clock, Test, and Power Pins
VDD_3.3V
VDD_2.5V
Pin Name
TEST_IN
RESET
MCLK
TRST
TMS
TDO
TCK
VSS
TDI
Zarlink Semiconductor Inc.
PWR
PWR
GND
I/O
MT90528
O
I
I
I
I
I
I
I
27
3.3 V, 4 mA
Schmitt PU
CMOS PU
CMOS PU
CMOS PU
CMOS
CMOS
Type
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Master Clock.
This signal drives the internal logic. The same
clock should be driven to the external memory
Chip reset signal (active LOW).
Note that internal reset activity is synchronous to
MCLK; this signal is latched internally and held,
and MCLK must be applied to bring the MT90528
out of reset.
The TRST pin (JTAG reset) should also be
asserted LOW during chip reset. Also see RESET
bit in Chip Wide Reset Register at address 0000h.
JTAG Test Mode Select.
JTAG Test Clock.
JTAG Test Data In.
Should be pulled HIGH if boundary-scan not in use.
JTAG Test Reset input (active LOW).
Should be asserted LOW on power-up and during
reset. Must be HIGH for JTAG boundary-scan
operation. Note: This pin has an internal pull-up
and must be pulled down externally for normal
operation.
JTAG Test Data Out.
Test input pins.
These pins must be grounded.
Power for I/O logic (3.3 V).
Power for core logic.
Ground for device.
Description
Data Sheet