MT90528AG ZARLINK [Zarlink Semiconductor Inc], MT90528AG Datasheet - Page 104

• Manufacturer Part Number: MT90528AG
• Description: 28-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

preceding section. There is not any additional circuitry within the Clock Management module since the RX_SAR is
responsible for providing the information required by the PLL.
Explanation of Operation: The UDT RX_SAR or the SDT RX_SAR generates a digital phaseword based on the
fill-level of the UDT/SDT Reassembly Circular Buffers of the MT90528. The PLL compares the phaseword with an
average value for the buffer fill of the Reassembly Circular Buffer in question. The PLL then adjusts the TDM output
clock accordingly. As mentioned previously, the phaseword of the Reassembly Circular Buffer is transmitted to the
Clock Management module by the RX_SAR. In the case of a slip, the phaseword is set to a pre-determined value
within the RX_SAR module. In such a case, the phaseword indicates to the PLL the type of slip which occurred (i.e.,
underrun or overflow) so that the PLL can adjust the clock rate appropriately. In the case of a cut VC (i.e., no cells
are arriving at the RX_SAR) or upon initialization, the phaseword is set in such a way that the PLL does not adjust
the TDM output clock.
More explanation regarding phaseword generation can be found in Section , “Digital Phaseword Generation for
Adaptive Clock Recovery,” on page 87.
4.7.2.7
There is a separate Stratum 4 digital PLL for each of the 28 ports in the MT90528 device. This module takes care of
generating several network clocks with the appropriate quality. The same PLL is used for clock recovery from TDM
clocks, network clocks, SRTS data, or buffer pointer data in adaptive mode.
In all modes of operation (explained below), the PLL is capable of generating an output clock of 1.544 MHz,
2.048 MHz, or 4.096 MHz. The frequency generated is determined by the PLL_FREQ_SEL bits in the per-port
Clocking Configuration Registers.
Architecture
A digital PLL must provide a clock synchronous to some input signal. Since there are several types of incoming
signals to synchronize to, the per-port PLLs require dedicated phase detectors for the various types of input. The
basic PLL architecture, however, is the same for all situations. It consists of a phase detector, a loop filter, a digital
controlled oscillator and a divider (see Figure 43).
Internal Digital PLL Sub-Module
RX_SAR
Module
Phaseword
Figure 42 - Adaptive Clock Recovery Sub-module
Zarlink Semiconductor Inc.
Clock Management Module
Digital PLL (refer
MT90528
Section 4.7.2.7
for details)
104
to
TDM Sub-Module”
Clocking Circuit”
To “Interface to
PLLCLK (ACM)
Multiplexers &
“Synchronous
Multiplexers
Data Sheet