MT90528AG ZARLINK [Zarlink Semiconductor Inc], MT90528AG Datasheet - Page 147

• Manufacturer Part Number: MT90528AG
• Description: 28-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 4010 (Hex)
Label: UFS
Reset Value: 0030 (Hex)
Address: 4012 (Hex)
Label: USR
Reset Value: 0000 (Hex)
CELL_CNT_ROLL
Address: 4014 (Hex)
Label: USER
Reset Value: 0000 (Hex)
CELL_CNT_ROLL
UTO_OUT_FIFO_
UTO_OUT_FIFO
PARITY_ROLL_
PARITY_ROLL_
UTO_IN_FIFO_
UTO_IN_FIFO_
_STATUS
Reserved
Reserved
Reserved
STATUS
EMPTY
EMPTY
Label
Label
Label
FULL
FULL
_SE
SE
Position
Position
Position
15:7
15:2
15:2
Bit
Bit
Bit
3
4
5
6
0
1
0
1
R/O/L
R/O/L
Type
Type
Type
R/W
R/W
R/O
R/O
R/O
R/O
R/O
R/O
R/O
Table 71 - UTOPIA Service Enable Register
Table 69 - UTOPIA FIFO Status Register
Table 70 - UTOPIA Status Register
If set, this bit indicates that the outgoing UTOPIA FIFO is full.
If set, this bit indicates that the outgoing UTOPIA FIFO is empty.
If set, this bit indicates that the incoming UTOPIA FIFO is empty.
If set, this bit indicates that the incoming UTOPIA FIFO is full.
Always reads “0000_0000_0”.
If set, this status bit indicates that the UTOPIA interface has received 2
by the UTOPIA Incoming Cell Counter at 4016h.
If set, this status bit indicates that the UTOPIA interface has received 2
taining parity errors, as counted by the UTOPIA Parity Mismatches Register at 400Eh.
Always reads “0000_0000_0000_00”.
When set, a ‘1’ on CELL_CNT_ROLL_STATUS will cause the UTOPIA_SRV bit to be set
in the Main Status Register at 0002h.
When set, a ‘1’ on PARITY_ROLL_STATUS will cause the UTOPIA_SRV bit to be set in
the Main Status Register at 0002h.
Always reads “0000_0000_0000_00”.
Zarlink Semiconductor Inc.
MT90528
147
Description
Description
Description
16
16
cells, as counted
data words con-
Data Sheet