ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet
ZL50020GAC
Related parts for ZL50020GAC
ZL50020GAC Summary of contents
Page 1
... MODE_4M0 MODE_4M1 Figure 1 - ZL50020 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. Enhanced 2 K Digital Switch ZL50020GAC ZL50020QCC ZL50020QCG1 ZL50020GAG2 **Pb Free Tin/Silver/Copper • Per-channel ITU-T G.711 PCM A-Law/µ-Law Translation • ...
Page 2
Per-channel high impedance output control • Per-channel message mode • Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses • Connection memory block programming • Supports ST-BUS and GCI-Bus standards for input and output timing • IEEE-1149.1 (JTAG) ...
Page 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Figure 1 - ZL50020 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Table 1 - CKi and FPi Configurations for Divided Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
Changes Summary The following table captures the changes from January 2006 to November 2006. Page Item 1 The following table captures the changes from the October 2004 issue. Page Item 13 Pin Description “CKi” on page 13 32 11.3, “Output ...
Page 8
Pinout Diagrams 1.1 BGA Pinout STi29 STi28 STi27 STi25 SS B STi31 STi10 STi5 STi4 CKo2 C STi30 STi9 V STi7 STi6 SS D STi17 STi11 V STi3 STi2 DD_IO E STi16 ...
Page 9
QFP Pinout 192 190 188 186 184 182 180 178 STi28 STi29 194 VDD_IO STi30 196 STi31 STi_8 198 VSS STi_9 200 STi_10 STi_11 202 STi_12 STi_13 204 STi_14 STi_15 206 VDD_IO IC_GND 208 VSS IC_Open 210 RESET TDo ...
Page 10
Pin Description PBGA Pin LQFP Pin Pin Name Number Number E6, E11, F6, 19, 33, V DD_CORE F7, F10, 45, 83, F11, L6, L7, 95, 109, L10, L11, 146, 173, M6, M7, 213, 233 M10, M11 H4, K5, B9, ...
Page 11
PBGA Pin LQFP Pin Pin Name Number Number K3 234 TMS L4 238 TCK L3 239 TRST M3 240 TDi G5 212 TDo B12, B13, 80, 105, IC_Open C10, C11, 150, 151, F13, G4, 152, 153, K12, C12, 210, 149 ...
Page 12
PBGA Pin LQFP Pin Pin Name Number Number A8, A9, A14, 61, 62, NC A15, E10, 63, 64, M2, N2, P2, 65, 66, P16, R2, 67, 68, R16, T6, T7, 134, 135, T8, T9, T10, 136, 137, T11, T12, 138, ...
Page 13
PBGA Pin LQFP Pin Pin Name Number Number B10 155 FPi B11 154 CKi B6, C6, D5, 179, 180, STi0 - 31 D4, B4, B3, 181, 182, C5, C4, E3, 183, 184, C2, B2, D2, 185, 187, F3, F4, E2, ...
Page 14
PBGA Pin LQFP Pin Pin Name Number Number N4, P4, R4 STio0 - 31 P5, N13, 10, 51, P11, R14, 52, 53, R15, M15, 54, 70, L15, L13, 72, 73, L14, E14, 74, 115, D13, D15, 116, ...
Page 15
PBGA Pin LQFP Pin Pin Name Number Number N12 44 DTA_RDY R11 40 CS N11 39 R/W_WR R12 42 DS_RD K13, K15, 82, 84 K14, J11, 86, 87, J12, J13, 88, 89, J15, H11, 90, 91, J14, ...
Page 16
Device Overview The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31). STio0 - 31 can also be configured as bi-directional pins, in which case STi0 - 31 will be ignored ...
Page 17
Mbps (256 channels per stream), this would result in 8192 channels. Memory limitations prevent the device from operating at this capacity. A maximum capacity of 2048 channels will occur if eight of the streams ...
Page 18
The ZL50020 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the negative input clock format ...
Page 19
FPi (61 ns) FPINP = 0 FPINPOS = 0 FPi (61 ns) FPINP = 1 FPINPOS = 0 FPi (61 ns) FPINP = 0 FPINPOS = 1 FPi (61 ns) FPINP = 1 FPINPOS = 1 CKi (16.384 MHz) CKINP ...
Page 20
FPo0 pulse width CKo0 FPo1 pulse width CKo1 FPo2 pulse width CKo2 FPo3 pulse width CKo3 The output timing is dependent on the operation mode that is selected. When the device is in Divided Clock mode, the frequencies on CKo0 ...
Page 21
CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 1 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 1 CKOFPO1EN = 1 CKO1P ...
Page 22
CKOFPO3EN = 1 CKOFPO3SEL1 FPO3P = 0 FPO3POS = 0 CKOFPO3EN = 1 CKOFPO3SEL1 FPO3P = 1 FPO3POS = 0 CKOFPO3EN = 1 CKOFPO3SEL1 FPO3P = 0 FPO3POS = 1 CKOFPO3EN = 1 CKOFPO3SEL1-0 ...
Page 23
Input Bit Delay Programming The input bit delay programming feature provides users with the flexibility of handling different wire delays when designing with source streams for different devices. By default, all input streams have zero bit delay, such that ...
Page 24
Input Bit Sampling Point Programming In addition to the input bit delay feature, theZL50020 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits the Stream Input Control Register ...
Page 25
The input delay is controlled by STIN[n]BD2-0 (bits control the bit shift and STIN[n]SMP1 - 0 (bits control the sampling point in the Stream Input Control Register (SICR0 - ...
Page 26
Output Advancement Programming This feature is used to advance the output data of individual output streams with respect to the output frame boundary. Each output stream has its own bit advancement value which can be programmed in the Stream ...
Page 27
Fractional Output Bit Advancement Programming In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on ...
Page 28
External High Impedance Control Advancement The external high impedance signals can be programmed to better match the timing required by the external buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit ...
Page 29
In variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams input channel number n = output channel number T = Delay between input and output For ...
Page 30
Frame N STi L-2 L-1 CH0 CH1 CH2 CH3 STio L-2 L-1 CH0 CH1 CH2 CH3 STi L-2 L-1 CH0 CH1 CH2 CH3 STio L-2 L-1 CH0 CH1 CH2 CH3 L = last channel = 31, 63, 127, or 255 ...
Page 31
Connection Memory Block Programming This feature allows for fast initialization of the connection memory after power up. 10.1 Memory Block Programming Procedure 1. Set MBPE (bit 3) in the Control Register (CR) from low to high. 2. Configure BPD2 ...
Page 32
Table 7, “ZL50020 Operating Modes” on page 32 summarizes the different modes of operation available within the ZL50020. Each Major mode (explained below) has an associated Minor mode that is determined by setting the MODE_4M Input Control pins and the ...
Page 33
Microprocessor Port The device provides access to the internal registers, connection memories and data memories via the microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed microprocessors. The microprocessor port consists of a 16-bit ...
Page 34
Software Reset In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset SRSTSW (bit 1) in the Software Reset Register (SRR). 14.0 Pseudo Random Bit Generation and Error Detection ...
Page 35
PCM A-law/µ-law Translation The ZL50020 provides per-channel code translation to be used to adapt pulse code modulation (PCM) voice or data traffic between networks which use different encoding laws. Code translation is valid in both Connection Mode and Message ...
Page 36
When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or ...
Page 37
Instruction Register The ZL50020 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its ...
Page 38
Register Address Mapping Address CPU A13 - A0 Access 0000 R/W Control Register H 0001 R/W Internal Mode Selection Register H 0002 R/W Software Reset Register H 0003 R/W Output Clock and Frame Pulse Control Register H 0004 R/W ...
Page 39
Detailed Register Description External Read/Write Address: 0000 H Reset Value: 0000 OPM Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to ...
Page 40
External Read/Write Address: 0000 H Reset Value: 0000 OPM Bit Name 2 OSB Output Stand By Bit: This bit enables the STio0 - 31 and the STOHZ0 -15 serial outputs. ...
Page 41
External Read/Write Address: 0001 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 8 ...
Page 42
External Read/Write Address: 0001 H Reset Value: 0000 Bit Name BPD2 - 0 Block Programming Data These bits refer to the value to be ...
Page 43
External Read/Write Address: 0002 H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits MUST be set to zero. 1 SRSTSW Software ...
Page 44
External Read/Write Address: 0003 H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits MUST be set to zero. 8 ...
Page 45
External Read/Write Address: 0004 H Reset Value: 0000 CKO CKO CKO3 FPO3 FPO3 P SEL1 SEL0 Bit Name Unused Reserved In normal functional mode, these bits MUST be set ...
Page 46
External Read/Write Address: 0004 H Reset Value: 0000 CKO CKO CKO3 FPO3 FPO3 P SEL1 SEL0 Bit Name 5 CKO1P Output Clock (CKo1) Polarity Selection When this bit is low, the output ...
Page 47
External Read/Write Address: 0005 - 0007 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to ...
Page 48
External Read Address: 0010 H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits are zero. 1 OUTERR Output Error (Read Only) ...
Page 49
External Read/Write Address: 00012 H Reset Value: 0000 BER BER BER BER BER F31 F30 F29 F28 F27 Bit Name BERF[n] BER Error Flag[n]: If BERF[n] is high, it indicates that ...
Page 50
External Read Address: 00014 H Reset Value: 0000 BER BER BER BER BER L31 L30 L29 L28 L27 Bit Name BERL[n] BER Receiver Lock[n]: If BERL[n] is high, it indicates that ...
Page 51
External Read/Write Address: 0100 - 011F H H Reset Value: 0000 Bit Name STIN[n]DR3 - 0 Input Data Rate Selection Bits: Note: ...
Page 52
External Read/Write Address: 0120 - 013F H H Reset Value: 0000 STIN[n] STIN[n] STIN[n] Q3C2 Q3C1 Q3C0 Bit Name Unused Reserved In normal functional mode, these ...
Page 53
External Read/Write Address: 0120 - 013F H H Reset Value: 0000 STIN[n] STIN[n] STIN[n] Q3C2 Q3C1 Q3C0 Bit Name STIN[n]Q1C2 - 0 Quadrant Frame 1 Control ...
Page 54
External Read/Write Address: 0200 - 021F H H Reset Value: 0000 STOHZ STOHZ [n]A2 [n]A1 Bit Name Unused Reserved In normal functional mode, these bits MUST ...
Page 55
External Read/Write Address: 0300 - 031F H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits MUST be set to ...
Page 56
External Read/Write Address: 0340 - 035F H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits MUST be set to zero. 1 ...
Page 57
Memory 20.1 Memory Address Mappings When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit the Control Register determine the access to the data or connection memory (CM_L ...
Page 58
UA V/C SSA SSA SSA Bit Name 14 V/C Variable/Constant Delay Control When this bit is low, the output data for this channel will be taken from con- stant delay memory. When ...
Page 59
Bit Name PCC1 - 0 Per-Channel Control Bits These two bits control the corresponding entry’s value on the STio stream. 0 CMM = 1 Connection Memory ...
Page 60
Bit Name 4 V/D Voice/Data Control When this bit is low, the corresponding channel is for voice. When this bit is high, the corresponding channel is for data. ...
Page 61
DC Parameters Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage 2 Core Supply Voltage 3 Input Voltage 4 Input Voltage (5 V-tolerant inputs) 5 Continuous Current at Digital Outputs 6 Package Power Dissipation 7 Storage Temperature * Exceeding these ...
Page 62
AC Parameters † AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure ...
Page 63
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Read Access Characteristics 1 CS de-asserted time 2 DS de-asserted time 3 CS setup to DS falling 4 R/W setup to DS falling 5 Address setup to DS falling 6 ...
Page 64
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Write Access Characteristics 1 CS de-asserted time 2 DS de-asserted time 3 CS setup to DS falling 4 R/W setup to DS falling 5 Address setup to DS falling 6 ...
Page 65
AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Read Access Characteristics 1 CS de-asserted time 2 RD setup to CS falling 3 WR setup to CS falling 4 Address setup to CS falling 5 RD hold after CS ...
Page 66
AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Write Access Characteristics 1 CS de-asserted time 2 WR setup to CS falling 3 RD setup to CS falling 4 Address setup to CS falling 5 Data setup to CS ...
Page 67
AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 TCK Clock Pulse Width Low 4 TMS Set-up Time 5 TMS Hold Time 6 TDi Input Set-up Time 7 ...
Page 68
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz) Characteristic 1 FPi Input Frame Pulse Width 2 FPi Input Frame Pulse Setup Time 3 FPi Input Frame Pulse Hold Time 4 CKi Input ...
Page 69
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 10 (4.096 MHz) Characteristic 1 FPi Input Frame Pulse Width 2 FPi Input Frame Pulse Setup Time 3 FPi Input Frame Pulse Hold Time 4 CKi Input ...
Page 70
AC Electrical Characteristics - ST-BUS/GCI-Bus Input Timing Characteristic 1 STi Setup Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 2 STi Hold Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps † Characteristics are over recommended operating conditions ...
Page 71
FPi CKi (16.384 MHz) t STi0 - 31 Bit1 Bit0 Bit7 Ch255 Ch255 Ch0 16.384 Mbps Input Frame Boundary Figure 28 - ST-BUS Input Timing Diagram when Operated at 16 Mbps FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi ...
Page 72
FPi CKi (16.384 MHz) STi0 - 31 Bit6 Bit7 Ch255 Ch255 16.384 Mbps Input Frame Boundary Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps † AC Electrical Characteristics - ST-BUS/GCI-Bus Output Timing Characteristic 1 STio Delay ...
Page 73
FPo0 CKo0 (4.096 MHz) STio0 - 31 Bit0 2.048 Mbps Ch31 STio0 - 31 Bit0 4.096 Mbps Ch63 t SOD8 STio0 - 31 Bit0 Bit7 Ch127 Ch0 8.192 Mbps t SOD16 STio0 - 31 Bit2 Bit1 Bit0 Bit7 Ch255 Ch255 ...
Page 74
AC Electrical Characteristics - ST-BUS/GCI-Bus Output Tristate Timing Characteristic 1 STio Delay - Active to High-Z 2 STio Delay - High-Z to Active 3 Output Drive Enable (ODE) Delay - High-Z to Active CKi @ 4.096 MHz CKi @ ...
Page 75
AC Electrical Characteristics - Clock Mode Input/Output Frame Boundary Alignment Characteristic 1 Input and Output Frame Offset in Divided Clock Mode 2 Input and Output Frame Offset in Multiplied Clock Mode † Characteristics are over recommended operating conditions unless ...
Page 76
FPo0/3 CKo0/3 Output Frame Boundary † AC Electrical Characteristics - FPo0/CKo0 and FPo3/CKo3 (4.096 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less than Input Cycle to Cycle Variation Characteristic 1 FPo0 Output Pulse ...
Page 77
FPo1/3 CKo1/3 Output Frame Boundary † AC Electrical Characteristics - FPo1/CKo1 and FPo3/CKo3 (8.192 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less than Input Cycle to Cycle Variation Characteristic 1 FPo1 Output Pulse ...
Page 78
FPo2/3 CKo2/3 Output Frame Boundary † AC Electrical Characteristics - FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less than Cycle to Cycle Variation on CK Characteristic 1 FPo2 Output ...
Page 79
FPo3 CKo3 Output Frame Boundary † AC Electrical Characteristics - FPo3/CKo3 (32.768 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less than Cycle to Cycle Variation on CKi Characteristic 1 FPo3 Output Pulse Width ...
Page 80
AC Electrical Characteristics - Divided Clock Mode Output Timing Characteristic 1 CKo0 to CKo1 (8.192 MHz) delay 2 CKo0 to CKo2 (16.384 MHz) delay 3 CKo0 to CKo3 (16.384 MHz/8.192 MHz/4.096 MHz) delay † Characteristics are over recommended operating ...
Page 81
Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
Page 82
Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
Page 83
For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...