ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 23

• Manufacturer Part Number: ZL50020GAC
• Description: Enhanced 2 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.1
The input bit delay programming feature provides users with the flexibility of handling different wire delays when
designing with source streams for different devices.
By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame
boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream
Input Control Register 0 - 31 (SICR0 - 31) as described in Table 24 on page 50. The input bit delay can range from
0 to 7 bits.
FPi
STi[n]
Bit Delay = 0
(Default)
STi[n]
Bit Delay = 1
Input Bit Delay Programming
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, and 8.192 and 16.384 Mbps modes respectively.
4 3
5
Last Channel
Last Channel
4 3
2 1 0
Figure 11 - Input Bit Delay Timing Diagram (ST-BUS)
2 1 0
7
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2
7
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3
Channel 0
Bit Delay = 1
Channel 0
Zarlink Semiconductor Inc.
ZL50020
23
Channel 1
Channel 1
Channel 2
Channel 2
Data Sheet