ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 70
ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
- Current page: 70 of 83
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† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
AC Electrical Characteristics
1
2
(16.384 MHz)
STi Setup Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
STi Hold Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
Input Frame Boundary
(4.096 MHz)
(8.192 MHz)
2.048 Mbps
4.096 Mbps
8.192 Mbps
STi0 - 31
STi0 - 31
STi0 - 31
CKi
CKi
FPi
CKi
FPi
FPi
Characteristic
Figure 27 - ST-BUS Input Timing Diagram when Operated at 2, 4, 8 Mbps
Ch127
Bit1
Ch31
Bit0
Ch63
Bit0
Ch127
Bit0
†
- ST-BUS/GCI-Bus Input Timing
Ch0
Bit7
t
Sym.
t
SIS8
t
t
t
t
t
t
t
SIH16
SIS16
SIS2
SIS4
SIS8
SIH2
SIH4
SIH8
Bit7
Ch0
Bit6
Ch0
Zarlink Semiconductor Inc.
t
SIH8
t
SIS4
ZL50020
Min.
5
5
5
5
8
8
8
8
t
SIH4
Bit5
Ch0
70
Ch0
Bit7
Typ.
Ch0
Bit6
t
SIS2
Ch0
Bit4
‡
t
SIH2
Max.
Ch0
Bit3
Units
Ch0
Bit5
ns
ns
ns
ns
ns
ns
ns
ns
Ch0
Bit2
Bit1
Ch0
Ch0
Bit6
Test Conditions
Bit4
Ch0
Bit0
Ch0
Data Sheet
V
V
V
V
CT
CT
CT
TT
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