ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 40
![no-image](/images/no-image-200.jpg)
ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
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1 - 0
External Read/Write Address: 0000
Reset Value: 0000
Bit
2
15
0
14
0
MS1 - 0
Name
OSB
H
13
0
Output Stand By Bit:
This bit enables the STio0 - 31 and the STOHZ0 -15 serial outputs. The following table
describes the HiZ control of the serial data outputs:
Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to
SOCR0 - 31 (bit2 - 0).
Memory Select Bits
These two bits are used to select connection memory low, connection high or data mem-
ory for access by CPU:
12
0
RESET
Table 13 - Control Register (CR) Bits (continued)
H
Pin
OPM
0
1
1
1
1
11
MS1 - 0
SRSTSW
10
(in SRR)
00
01
10
11
0
X
1
0
0
0
FPIN
POS
Zarlink Semiconductor Inc.
9
ZL50020
ODE
CKINP
Pin
X
X
0
1
1
8
40
Connection Memory High Read/Write
Connection Memory Low Read/Write
OSB
FPINP
Bit
X
X
X
0
1
7
Description
Data Memory Read
Memory Selection
(Controlled by CM)
CKIN
6
1
Reserved
STio0 - 31
Active
CKIN
HiZ
HiZ
HiZ
HiZ
5
0
VAR
EN
4
MBPE
3
(Controlled by CM)
STOHZ0 - 15
Driven High
Driven High
Driven High
Driven High
OSB
2
Active
Data Sheet
MS1
1
MS0
0
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