AM79C03 AMD [Advanced Micro Devices], AM79C03 Datasheet - Page 25

• Manufacturer Part Number: AM79C03
• Description: Dual Subscriber Line Audio Processing Circuit (DSLAC) Devices
• Manufacturer: AMD [Advanced Micro Devices]

Command Description and Formats
Microprocessor Interface Description
A microprocessor may be used to program the DSLAC
device and control its operation using the Microproces-
sor Interface (MPI). Data programmed previously may
be read out for verification. For each channel, com-
mands are provided to assign values to the following
parameters.
– Transmit time slot
– Receive time slot
– Transmit clock slot
– Receive clock slot
– Transmit gain
– Receive loss
– B-filter coefficients
– X-filter coefficients
– R-filter coefficients
– Z-filter coefficients
– Adaptive B filter parameters
– AISN coefficient
– Read/Write SLIC Input/Output
– Select A-law or µ-law code
– Select Transmit PCM Port A or B
– Select Transmit PCM clock edge
– Select Transmit PCM delay
– Select Receive PCM Port A or B
– Enable/disable B filter
– Enable/disable Z filter
– Enable/disable X filter
– Enable/disable R filter
– Enable/disable GX filter
– Enable/disable GR filter
– Enable/disable AX amplifier
– Enable/disable AR amplifier
– Enable/disable adaptive B filter
– Select test modes
– Select Active or Inactive (standby) mode
SLAC Products
The following description of the MPI is valid for either
Channel 1 or 2. Whenever CS is specified, it refers to
either CS1 or CS2. If desired, both channels may be
programmed simultaneously with identical information
by activating CS1 and CS2 at the same time. Com-
mands that affect both channels simultaneously are not-
ed as such.
The MPI consists of serial data input (DIN or DIO), out-
put (DOUT or DIO), data clock (DCLK), and a separate
chip select (CS1 and CS2) input for each channel. The
serial input consists of 8-bit command words that may
be followed with additional bytes of input data or may
be followed by the DSLAC device sending out bytes of
data. All data input and output is MSB (D7) first and LSB
(D0) last. All data bytes are read or written one at a time,
with CS going High for at least the minimum off period
before the next byte is read or written.
All commands that require additional input data to the
device must have the input data as the next N words
written into the device (for example, framed by the next
N transitions of CS). All commands that are followed
by output data causes the device to output data for the
next N transitions of CS going Low. The DSLAC device
does not accept any input commands until all the data
is shifted out. Unused bits in the data bytes are read
out as zeros.
A command sequence to one channel must be finished
before a command can be sent to the channel. The NOP
Command 2 is recommended to follow any set of com-
mands to the DSLAC device. The NOP is executed in
the event of any anamolous CS assertion.
An MPI cycle is defined by transitions of CS and DCLK.
If the CS lines are held in the High state between ac-
cesses, the DCLK may run continuously with no change
to the internal control data. Using this method, the same
DCLK may be run to a number of DSLAC devices and
the individual CS lines selects the appropriate device
to access. Between command sequences, DCLK can
stay in the High state indefinitely with no loss of internal
control information regardless of any transitions on the
CS lines. Between bytes of a multibyte read or write
command sequence, DCLK also can stay in the High
state indefinitely; however, each low-going transition of
the CS line still advances the byte counter. DCLK can
stay in the Low state indefinitely with no loss of internal
control information, provided the CS lines remain at a
high level.
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