AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 72
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AM79C850KCW
Manufacturer Part Number
AM79C850KCW
Description
SUPERNET-R 3
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C850KCW.pdf
(97 pages)
- Current page: 72 of 97
- Download datasheet (346Kb)
SUPERNET 3 Programmable Registers (continued)
72
“vector_length”
AMD
“le_threshold”
“xmit_vector”
“plc_cntrl_a”
“plc_cntrl_b”
Mnemonic
“intr_mask”
“unlckdly”
Register
“fifoflag”
“imsk3l”
“swpr2”
“ltdpa1”
“earv2”
“lwpr1”
“lrwd1”
“lwpr2”
“lrwd2”
“wpr2”
“lsa0”
“rpr2”
“imr”
“lss”
“ivr”
“6d”
“6e”
“74”
“75”
“76”
“77”
“78”
“7c”
“7d”
“7e”
“ilr”
“7f”
NPADDR7–0
“64”
“65”
“66”
“67”
“68”
“69”
“6a”
“6b”
“6c”
“6d”
“6e”
“70”
“71”
“72”
“73”
“74”
“75”
“76”
“77”
“78”
“79”
“7a”
“7b”
“7c”
“7d”
“7e”
“80”
“81”
“82”
“83”
“84”
“85”
“6f”
“7f”
Description
Lower 16 bits of IMSK register 3
Interrupt Vector register (Read Only)
Interrupt mask register
(Hidden)
Read pointer for second receive queue
Write pointer for second receive queue
Shadow write pointer for second receive queue
End Address of Receive 2 Queue
Auto Unlock Delay Register
(Hidden)
(Hidden)
(Hidden)
(Hidden)
(Hidden)
Last Transmit Descriptor Pointer for Async 1 queue
(Hidden)
(Hidden)
PLC–S control register A
PLC–S control register B
PLC–S interrupt mask register
PLC–S transmit vector register
PLC–S vector length register
PLC–S link error threshold register
P R E L I M I N A R Y
SUPERNET 3
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