AM79C940KCW AMD [Advanced Micro Devices], AM79C940KCW Datasheet - Page 78
AM79C940KCW
Manufacturer Part Number
AM79C940KCW
Description
Media Access Controller for Ethernet (MACE)
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C940KCW.pdf
(122 pages)
- Current page: 78 of 122
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Programmer’s Register Model (continued)
78
Addr
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AMD
Mnemonic
PHYCC
RCVCC
CHIPID
CHIPID
RNTPC
PLSCC
LADRF
PADR
MPC
UTR
IAC
—
—
—
—
—
Physical Layer Signalling (PLS) Configuration Control
08
06
01
Physical Layer (PHY) Configuration Control
80
40
20
10
08
04
02
01
Chip Identification Register LSB—CHIPID [7:0]
Chip Identification Register MSB—CHIPID [15:8]
Internal Address Configuration
80
40
20
10
08
04
04
02
01
Reserved
Logical Address Filter—8 bytes—8 reads or writes—LS Byte first
Physical 6 bytes—6 reads or writes—LS Byte first
Reserved
Reserved
Missed Packet Counter—Number of receive packets missed
Reserved
Runt Packet Count—Number of runt packets addressed to this node
Receive Collision Count—Number of receive collision frames on network
Reserved
User Test Register
80
40
20
10
08
06
XMTSEL
PORTSEL [1:0]—Port Select (2 bits)
00
01
10
11
ENPLSIO Enable Status
LNKFL
DLNKTST Disable Link Test—Force 10BASE-T port into Link Pass
REVPOL
DAPC
LRT
ASEL
RWAKE
AWAKE
ADDRCHG Address Change—Write to PHYADDR or LOGADDR after ENRCV
—
—
—
—
—
PHYADDR Reset Physical Address pointer
LOGADDR Reset Logical Address pointer
—
RTRE
RTRD
RPA
FCOLL
RCVFCSE Receive FCS Enable
LOOP
00
01
10
11
01
Transmit Mode Select: 1 DO = 1 during IDLE
Link Fail—Reports 10BASE-T receive inactivity
Reversed Polarity—Reports 10BASE-T receiver wiring error
Disable Auto Polarity Correction—Detection remains active
Low Receive Threshold—Extended distance capability
Auto Select—Select 10BASE-T port when active, otherwise AUI
Remote Wake—10BASE-T, AUI and EADI features active during sleep
Auto Wake—10BASE-T receive and LNKST active during sleep
Reserved Test Register Enable— must be 0
Reserved Test Register Disable
Runt Packet Accept
Force Collision
Loopback control (2 bits)
No loopback
External loopback
Internal loopback, excludes MENDEC
Internal loopback, includes MENDEC
—
AUI selected
10BASE-T selected
DAI port selected
GPSI selected
Am79C940
Contents
R/W
R/W
R/W
R/W
R/W
R/W
R/W
as 0
R/W
R/W
as 0
R/W
as 0
R/W
as 0
R/W
as 0
R/W
RO
RO
RO
RO
RO
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