ZL50404GDC ZARLINK [Zarlink Semiconductor Inc], ZL50404GDC Datasheet
ZL50404GDC
Related parts for ZL50404GDC
ZL50404GDC Summary of contents
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... Serial U EEPROM Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch ZL50404GDC • Failover Features • Rapid link failure detection using hardware-generated heartbeat packets • ...
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Per queue traffic shaper on uplink port • Packet Filtering and Port Security • Static address filtering for source and/or destination MAC • Static MAC address not subject to aging • Secure mode freezes MAC address learning (each port ...
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Description The ZL50404 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 4 ports at 10/100 Mbps, 1 uplink port at 10/100 Mbps, and a CPU interface for lightly managed and unmanaged switch ...
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BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ShortEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PVMAP00_3 – Port 0 Configuration Register ...
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TOSPML – TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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BMRCn - Port 0~3,8,9 Broadcast/Multicast Rate Control 13.3.9.3 PR100_n – Port 0~3 ...
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I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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BGA and Ball Signal Descriptions 1.1 BGA Views (Top-View SCLK DATAI DATAO STRO RSVD P_INT SDA SCL RSVD RSVD # C RESET TSTO TSTO TSTO TSTO OUT# UT1 UT3 ...
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Ball Signal Descriptions All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive. Notes # = Active low signal Input = Input signal Input-ST = Input signal with Schmitt-Trigger ...
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Ball Signal Description Table (continued) Ball No(s) Symbol N6, P6, R6, T6, N3, M[3:0]_TXD[3:0] P3, R3, T3, L4, L3, M2, M1, G4, H3, J2, J1 P7, E1, E3, E2 M[3:0]_COL T7, N2, M3, J3 M[3:0]_TXCLK P5, P2, K4, G3 M[3:0]_RXCLK ...
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Ball Signal Description Table (continued) Ball No(s) Symbol C12 TRST# B13 TCK B14 TMS D11 TDO D6 SCAN_EN System Clock, Power, and Ground Pins A1 SCLK D9, H4, H13, N7 D5, D12, E4, E13, M4 M13, ...
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Ball Signal Description Table (continued) Ball No(s) Symbol A12, B12, A11, B11, RSVD A10, B10, A9, B9, A8, B8, A7, B7, A6, B6, A5, B5, B4, L13, K14, L15, L16, N14, P14, R14, T14, N11, P11, R11, T11, N8, P8, ...
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Ball Signal Description Table (continued) Ball No(s) Symbol C6 TSTOUT[7] D7 TSTOUT[8] C7 TSTOUT[9] D8 TSTOUT[10] C8 TSTOUT[11] C9 TSTOUT[12] C11, C10, D10 TSTOUT[15:13] R5, R2, L2, H2 M[3:0]_TXEN 1. External pull-up/down resistors are required on all bootstrap pins for ...
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Signal Mapping and Internal Pull Up/Down Configuration The ZL50404 Fast Ethernet access ports (0-3) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to ...
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The ZL50404 Fast Ethernet uplink port (port 9) supports 1 interface option: MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” ...
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Bootstrap Options TSTOUT[15:0] and M[3:0]_TXEN pins serve as bootstrap pins during device power-up or reset. Please refer to “Typical Reset & Bootstrap Timing Diagram” on page 111 for more information on when the bootstrap pins are sampled. The bootstrap ...
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Block Functionality M GMAC Management Module 2.1 Internal Memory Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB), storing of MAC Control Table database (MCT), and the Network Management (NM) Database statistics counters and MIB. ...
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CPU MAC Module (CMAC) The CPU Media Access Control (CMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external CPU device. It support a register access mechanism via the serial interface. This ...
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Heartbeat Packet Generation and Response The ZL50404 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet generation module allows simultaneous tracking of all the RMAC ports. Periodically, a LHB ...
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Config Data Index Reg 1 Index Reg 0 Reg (Addr = 1) (Addr = 0) (Addr = 2) 16-bit Address 8-bit Data Bus Internal Registers Inderect Access 3.1 Register Configuration, Frame Transmission, and Frame Reception 3.1.1 Register Configuration The ZL50404 ...
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The ZL50404 supports special register-write in serial mode. This allows CPU to write to two consecutive configuration registers in a single write operation. By writing to bit[14] of configuration register address, CPU can write 16-bit data to address 010b. ...
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Specifically, there are the following types of control frames generated by the CPU and sent to the ZL50404: • Memory read request • Memory write request • Learn Unicast MAC address • Delete Unicast MAC address • Search Unicast MAC ...
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Address The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address. 3.2.3 Data ...
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An ABORT command is detected when DATAIN is sampled low when STROBE- rise and DATAIN is sampled high when STROBE- fall. 3.3.1 Write Command All registers in ZL50404 can be modified through this synchronous serial interface. Once the data has ...
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Data Forwarding Protocol 4.1 Unicast Data Frame Forwarding When a frame arrives assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. ...
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During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release ...
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Search, Learning, and Aging 5.3.1 MAC Search The search block performs source MAC address and destination MAC address searching indicated earlier match is not found, then the next entry in the linked list must be ...
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Quality of Service Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by some ...
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Priority Classification Rule Figure 7 shows the ZL50404 priority classification rule. TOS Precedence over VLAN? Yes Use VLAN priority Use Default port settings 5.9 Port Based VLAN An administrator can use the PVMAP Registers to configure the ZL50404 for ...
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For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming port (zero) denotes that an outgoing port is not eligible to receive a packet from an ...
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RxDMA The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 TxQ Manager First, the ...
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TotalAssured Goals Bandwidth (user defined) Highest 50 Mbps transmission priority, P3 Middle 37.5 Mbps transmission priority, P2 Low transmission 12.5 Mbps priority, P1 Total 100 Mbps A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved ...
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Strict Priority When strict priority is part of the scheduling algorithm queue has any frame to transmit, it goes first. For RMAC ports, this is an easy way to provide the different service. For all recognizable traffic, ...
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Also, when shaping is enabled possible for a queue to explode in length if fed by a greedy source. The reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending ...
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Buffer Management Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the ...
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Dropping When Buffers Are Scarce As already discussed, the WRED mechanism may drop frames on output queue status. In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer ...
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ZL50404 IETF Table 9 - Mapping to IETF Diffserv Classes for MMAC & CPU Ports As the table illustrates, the classes of Table 9 are merged in pairs— used for network management (NM) and expedited forwarding service (EF) ...
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Port Trunking See Port Trunking application note, ZLAN-48, for more information. 8.1 Features and Restrictions A port group (i.e. trunk) can include physical ports to form a fault tolerant link. There are eight trunk groups total. ...
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Source or Destination MAC address based 2. Flow based 3. Port based In source or destination mac address based mirroring, the “M” bit of the mirroring MAC address in the MCT is set. Also, the user need to specify ...
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Clocks 11.1 Clock Requirements 11.1.1 System Clock (SCLK) speed requirement SCLK is the primary clock for the ZL50404 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 1-5 ports ...
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If the RMAC ports are configured in Reverse GPSI mode, TXCLK and RXCLK are generated from M_CLK and are equal to M_CLK/2 for 10M mode. M_CLK needs MHz clock in this mode and USD must be ...
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Frames with Length Between 128-255 Bytes B[16] A-l B[17] A-u Frames with Length Between 256-511 Bytes B[18] B-l Frames with Length Between 512-1023 Bytes Frames with Length Between 1024-1528 Bytes B[19] B-u Fragments B[20] C-l Alignment Error B[21] C-U1 Undersize ...
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IEEE 802.3 HUB Management (RFC 1516) 12.2.1 Event Counters 12.2.1.1 ReadableOctet Counts number of bytes (i.e. octets) contained in good valid frames received. Frame size: No FCS (i.e. checksum) error No collisions 12.2.1.2 ReadableFrame Counts number of good valid ...
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FrameTooLongs Counts number of frames received with size exceeding the maximum allowable frame size. Frame size: FCS error: Framing error: No collisions 12.2.1.6 ShortEvents Counts number of frames received with size less than the length of a short event. ...
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VeryLongEvents Counts number of frames received with size larger than Jabber Lockup Protection Timer (TW3). Frame size: 12.2.1.11 DataRateMisatches For repeaters or HUB application only. 12.2.1.12 AutoPartitions For repeaters or HUB application only. 12.2.1.13 TotalErrors Sum of the following ...
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RMON – Ethernet Statistic Group (RFC 1757) 12.4.1 Event Counters 12.4.1.1 Drop Events Counts number of times a packet is dropped, because of lack of available resources. DOES NOT include all packet dropping -- for example, random early drop ...
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OversizePkts Counts number of frames received with size exceeding the maximum allowable frame size. Frame size: FCS error Framing error No collisions 12.4.1.8 Fragments Counts number of frames received with size less than 64 bytes and with bad FCS. ...
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Pkts1024to1518Octets for any packet with size from 1024 bytes to 1518 bytes Counts both good and bad packets. 12.5 Miscellaneous Counters In addition to the statistics groups defined in previous sections, the ZL50404 has other statistics counters for its own ...
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Register Definition 13.1 ZL50404 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..3,8,9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 ...
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Register MULTICAST_HASHn-1 Multicast hash result n mask byte 1 3. CPU Port Configuration MAC0 CPU MAC Address byte 0 MAC1 CPU MAC Address byte 1 MAC2 CPU MAC Address byte 2 MAC3 CPU MAC Address byte 3 MAC4 CPU MAC ...
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Register MCC Multicast Congestion Control MCCTH Multicast Congestion Threshold RDRC0 WRED Drop Rate Control 0 RDRC1 WRED Drop Rate Control 1 RDRC2 WRED Drop Rate Control 2 SFCB Share FCB Size C1RS Class 1 Reserve Size C2RS Class 2 Reserve ...
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Register USER_PORTn_LOW User Define Logical Port n Low USER_PORTn_HIGH User Define Logical Port n High USER_PORT1:0_ User Define Logic Port 0 PRIORITY and 1 Priority USER_PORT3:2_ User Define Logic Port 2 PRIORITY and 3 Priority USER_PORT5:4_ User Define Logic Port ...
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Register DEVICE Device id and test SUM EEPROM Checksum Register LHBTimer Link heart beat time out timer LHBReg0 LHB control field value[7:0] LHBReg1 LHB control field value [15:8] fMACCReg0 Forced MAC control field value [7:0] fMACCReg1 Forced MAC control field ...
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Register MIRROR_SRC_MAC4 Mirror Source MAC Address 4 MIRROR_SRC_MAC5 Mirror Source MAC Address 5 MIRROR_CONTROL Port Mirror Control Register RMAC_MIRROR0 RMAC Mirror 0 RMAC_MIRROR1 RMAC Mirror 1 8. Per Port QOS Control FCRn Flooding Control Register n BMRCn Broadcast/Multicast Rate Control ...
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Register MASK2 MASK Timeout 2 MASK3 MASK Timeout 3 MASK4 MASK Timeout 4 BOOTSTRAP[2:0] BOOTSTRAP Read Back PRTFSMSTn Ethernet Port n Status Read Back PRTQOSSTn RMAC Port n QOS and Queue Status PRTQOSST8A CPU Port QOS and Queue Status A ...
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Register BM_RLSFF_INFO2 Bm_rlsfifo_info[23:16] BM_RLSFF_INFO3 Bm_rlsfifo_info[31:24] BM_RLSFF_INFO4 Bm_rlsfifo_info[39:32] BM_RLSFF_INFO5 Fifo_cnt[2:0],Bm_rlsfifo_inf o[44:40] F. System Control GCR Global Control Register DCR Device Control Register DCR1 Device Control Register 1 DPST Device Port Status Register DTST Data read back register DA DA Register Table ...
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Directly Accessed Registers 13.2.1 INDEX_REG0 • Address for indirectly accessed register addresses (16 bits) • Address = 0 (write only) 13.2.2 DATA_FRAME_REG • Data of indirectly accessed registers (8 bits) • Address = 2 (read/write) 13.2.3 CONTROL_FRAME_REG • CPU ...
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When the CPU reads this register: Bit [0]: Control Frame receive buffer ready, CPU can write a new frame 1 – CPU can write a new control command 1 0 – CPU has to wait until this bit is ...
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Indirectly Accessed Registers 13.3.1 (Group 0 Address) MAC Ports Group 13.3.1.1 ECR1Pn: Port n Control Register I²C Address 000+n; CPU Address:0000+ port number) Accessed by CPU and I²C (R/W) Bit [ Flow Control Off 0 ...
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ECR2Pn: Port n Control Register I²C Address: 00A+n; CPU Address:0001+ port number) Accessed by CPU and I²C (R/W) Bit [0]: Filter untagged frame 0: Disable (Default) 1: All untagged frames from this port are discarded or follow ...
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ECR3Pn: Port n Control Register I²C Address: 014+n; CPU Address:0080+ port number) Accessed by CPU and I²C (R/W) Bit [0]: Enable receiving short frame < 64B 0: Disable (Default) 1: Allow receiving short frame with correct CRC. ...
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Bit [5]: Frame loopback. 0: Disable frame from sending back to its source port. (Default) 1: Allow frame to send back to its source port In a regular ethernet switch, a packet should never be receive and forwarded to the ...
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Bit [2]: Internal loopback. 0: Disable (Default) 1: Enable In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another ...
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Address) VLAN Group 13.3.2.1 AVTCL – VLAN Type Code Register Low I²C Address 028; CPU Address:h100 Accessed by CPU and I²C (R/W) Bit [7:0]: VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0) 13.3.2.2 AVTCH ...
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Bit [6]: Default Discard priority. Used when Bit [7]=1 0 – Discard Priority Level 0 (Lowest) (Default) 1 – Discard Priority Level 1(Highest) Bit [7]: Enable Fix Priority (Default Disable. All frames are analysed. Transmit Priority and ...
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Bit [7]: Enable logical port match in secure mode 0: Disable (Default) 1: Enable - When Well Known or User Define logical port force discard enabled, force any IP packet with logical port number matching logical port numbers to CPU. ...
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TRUNKn_HASH54 – Trunk group 0~7 hash result 5/4 destination port number CPU Address:h20A+ trunk group) Accessed by CPU (R/W) Bit [3:0] Hash result 4 destination port number (Default 0) Bit [7:4] Hash result 5 destination port number ...
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MULTICAST_HASHn-0 – Multicast hash result 0~7 mask byte 0 CPU Address:h228+ hash value) Accessed by CPU (R/W) Bit [3:0]: Port 3-0 bit map for multicast hash. (Default 0xF) Bit[7:4]: Reserved. (Default 0xF) 13.3.3.7 MULTICAST_HASHn-1 – Multicast hash ...
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MAC1 – CPU MAC address byte 1 CPU Address:h301 Accessed by CPU (R/W) Bit [7:0]: Byte 1 of the CPU MAC address (Default 0) 13.3.4.3 MAC2 – CPU MAC address byte 2 CPU Address:h302 Accessed by CPU (R/W) Bit ...
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Bit [2]: Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read Bit [6:3]: Reserved Bit [7]: Device Timeout Detected interrupt 13.3.4.8 INTP_MASK0 – Interrupt Mask for MAC Port 0,1 CPU Address:h310 Accessed by CPU (R/W) ...
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Bit [6]: Select Multicast Queue 2 Bit [7]: Select Multicast Queue 3 Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0). 13.3.4.11 RQSS – Receive Queue Status CPU Address:h324 Accessed by CPU (RO) CPU receive queue status Bit [3:0]: Unicast ...
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CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command CPU Address:h330-336 Accessed by CPU, (R/W) 55 CQ6 CQ5 CQ4 CPU Queue insertion command Bit[3:0]: Destination Map (port 3-0). Bit[7:4]: Reserved. Must be 0. Bit[9:8]: Destination Map (MMAC, CPU). Bit [13:10] ...
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CPU Queue insertion command Granule pointer. Bit [14:0]: Pointer valid Bit [15]: 13.3.4.18 CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status CPU Address:h33A-33E Accessed by CPU, (R/W) CR4 CR3 CR2 CPU Queue insertion command Header pointer Bit [14:0]: Tail pointer Bit ...
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AGETIME_HIGH –MAC address aging time High I²C Address h04A; CPU Address h401 Accessed by CPU and I²C (R/W) Bit [7:0]: High byte of the MAC address aging timer (Default 0) The default setting of AGETIME_LOW/HIGH provides 300 seconds aging ...
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Address) Buffer Control/QOS Group 13.3.6.1 QOSC – QOS Control I²C Address h04B; CPU Address:h500 2 Accessed by CPU and I C (R/W) Bit [0]: Enable TX rate control (on RMAC ports only) 1 – Enable 0 – ...
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MCCTH – Multicast Threshold Control CPU Address: 512 Accessed by CPU (R/W) Threshold on the multicast granule count. Exceeding the threshold consider as Bit [7:0]: multicast resource low and the new multicast will be dropped flow ...
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SFCB – Share FCB Size I²C Address h074, CPU Address 518 Accessed by CPU and I²C (R/W) Bits [7:0]: Expressed in multiples of 16 granules. Buffer reservation for shared pool. 13.3.6.9 C1RS – Class 1 Reserve Size I²C Address ...
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AVPMM – VLAN Priority Map I²C Address h057, CPU Address:h531 Accessed by CPU and I²C (R/W) Map VLAN priority into eight level transmit priorities: Bit [0]: Priority when the VLAN tag priority field is 2 (Default 0) Bit [3:1]: ...
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TOSPML – TOS Priority Map I²C Address h059, CPU Address:h540 Accessed by CPU and I²C (R/W) Map TOS field in IP packet into eight level transmit priorities Bit [2:0]: Priority when the TOS field is 0 (Default 0) Bit ...
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Bit [3]: Frame drop priority when TOS field is 3 (Default 0) Bit [4]: Frame drop priority when TOS field is 4 (Default 0) Bit [5]: Frame drop priority when TOS field is 5 (Default 0) Bit [6]: Frame drop ...
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Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_Enable can individually turn on/off each Well Known Port if desired. Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select ...
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WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority I²C Address h0AB, CPU Address 563 Accessed by CPU and I²C (R/W) Bits[3:0]: Priority setting, transmission + dropping, for Well known port 6 (22 for ssh) Bits[7:4]: Priority setting, transmission ...
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USER_PORT[7:0]_[LOW/HIGH] – User Define Logical Port 0~7 I²C Address h092+n(Low); CPU Address 570+2n(Low logical port number) I²C Address h09A+n(High); CPU Address 571+2n(High) Accessed by CPU and I²C (R/W) (Default 00) This register is duplicated eight times from ...
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USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority I²C Address h0A5, CPU Address 593 Accessed by CPU and I²C (R/W) Bits[3:0]: Priority setting, transmission + dropping, for logic port 6 Bits[7:4]: Priority setting, transmission + dropping, for ...
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RLOWL – User Define Range Low Bit 7:0 I²C Address h0AE, CPU Address: 5A0 Accessed by CPU and I²C (R/W) Bits[7:0]: Lower 8 bit of the User Define Logical Port Low Range 13.3.6.36 RLOWH – User Define Range Low ...
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Address) MISC Group 13.3.7.1 MII_OP0 – MII Register Option 0 I²C Address 0BC, CPU Address:h600 Accessed by CPU and I²C (R/W) Bit [4:0]: Vendor specified link status register address (null value means don’t use it) (Default 00). ...
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Bit [5]: Report to CPU 0 – Disable (Default) 1 – Enable When disable new MAC address report or aging reports are disable for all ports. When enable, register SE_OPMODE is used to enable/disable selectively each function. Bit [6]: MII ...
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MIIC3 – MII Command Register 3 CPU Address:h606 Accessed by CPU (R/W) Bits [4:0] PHY_AD – 5 Bit PHY Address Bit [5] Reserved Bit [6] VALID – Data Valid from PHY (Read Only) Bit [7] RDY – Data is ...
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DEVICE Mode CPU Address:h60A Accessed by CPU (R/W) Bit [0]: Reserved Bit [1]: CPU Interrupt Polarity 0: Negative Polarity 1: Positive Polarity (Default) Bit [7:2]: Reserved 13.3.7.12 CHECKSUM - EEPROM Checksum I²C Address 0FF, CPU Address:h60B Accessed by CPU ...
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MAC Control Frame OpCode CPU Address:h613, h614 Accessed by CPU (R/W) The registers define the operation code if MAC control frame is forced out by processor. 13.3.7.16 FCB Base Address Register 0 I²C Address 0BF, CPU ...
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MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0~5 CPU Address 700-705 Accessed by CPU (R/W) DEST_MAC5 DEST_MAC4 [47:40] [39:32] (Default 00) (Default 00) 13.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0~5 CPU Address 706-70B Accessed by CPU (R/W) SRC_MAC5 ...
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Address) Per Port QOS Control 13.3.9.1 FCRn – Port 0~3,8,9 Flooding Control Register I²C Address h04C+n; CPU Address:h800 port number) Accessed by CPU and I²C (R/W) Bit [3:0]: U2MR: Unicast to Multicast Rate. Units in ...
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PR100_CPU – Port CPU Reservation I²C Address h073, CPU Address 848 Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. (Default 0x6) 13.3.9.5 PRM – Port MMAC Reservation I²C Address h072, CPU Address 849 Accessed by ...
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QOSC16 - QOSC21 - Classes Byte Limit CPU port 2 Accessed by CPU and I C (R/W): • QOSC16 – BYTE_L11 Level 1 for queue 1 (I • QOSC17 – BYTE_L21 Level 2 for queue 1 (I • QOSC18 ...
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QOSC36 - QOSC39 - Shaper Control Port MMAC Accessed by CPU (R/W) W0 – QOSC36[7:0] – TOKEN_LIMIT_C00 (CPU Address 8A4) W1 – QOSC37[7:0] – TOKEN_LIMIT_C01 (CPU Address 8A5) W2 – QOSC38[7:0] – TOKEN_LIMIT_C02 (CPU Address 8A6) W3 – QOSC39[7:0] ...
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BOOTSTRAP0 – BOOTSTRAP3 CPU Address E80-E83 Accessed by CPU (RO BT3 Bit [15:0]: Bootstrap value from TSTOUT[15:0]: Bit [23:16]: Bootstrap value from M[3:0]_TXEN Bit [31:20]: Reserved 13.3.10.6 PRTFSMST0~3,8,9 CPU Address E90+n Accessed by CPU (RO) TX FSM ...
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PRTQOSST0-PRTQOSST3 CPU Address EA0+n Accessed by CPU (RO) Source port reservation low Bit [0]: No source port buffer left Bit [1]: Unicast congestion detected on best effort queue Bit [2]: Reserved Bit [3]: High priority queue reach L1 WRED ...
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PRTQOSST9A, PRTQOSST9B (MMAC port) CPU Address EAA – EAB Accessed by CPU (RO) 15 PQSTB Bit [0]: Source port reservation low Bit [1]: No source port buffer left Bit [2]: Unicast congestion detected on best effort queue Bit [3]: ...
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CLASSQOSST CPU Address EAC Accessed by CPU (RO) Bit [0]: No share buffer Bit [1]: No class 1 buffer Bit [2]: No class 2 buffer Bit [3]: No class 3 buffer Bit [7:4]: Reserved 13.3.10.11 PRTINTCTR CPU Address EAD ...
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QCTRL CPU Address EBA Accessed by CPU (R/W) Stop QM FSM at idle Bit [0]: Stop MCQ FSM at idle Bit [1]: Stop new granule grant to any source Bit [2]: Stop release granule from any source Bit [3]: ...
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Bit [5] Set 1 to reset the pools that are assigned Bit [7:6] Reserved If CPU wants to reset pools again, CPU has to clear bit 5 and then set bit 5. Note: Before CPU doing so, CPU should set ...
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CPU address EC6 Accessed by CPU (R/W) Bit [6:0] Fcb_number[14:8]. The total number of granules that CPU assigns. Bit [7] Set 1 to write If CPU wants to write again, CPU has to clear bit 15 and then set bit ...
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CPU address ECB Accessed by CPU (RO) Bit [5:0] Rls_tail_ptr[14:9] Bit [7:6] Rls_count[1:0] CPU address ECC Accessed by CPU (RO) Bit [4:0] Rls_count[6:2] Bit [ then It is multicast packet. Bit [7:6] Rls_src_port[1:0[ CPU address ECD Accessed by ...
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Bit [4]: Initialization Completed (Default = 0) This bit is reserved in unmanaged mode. In managed mode, the CPU writes this bit with ‘1’ to indicate initialization is completed and ready to forward packets. The ‘0' to '1' transition will ...
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DPST – Device Port Status Register CPU Address:hF03 Accessed by CPU (R/W) Bit [4:0]: Read back index register. This is used for selecting what to read back from DTST. (Default 00) - 5’b00000 - Port 0 Operating mode and ...
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Characteristics and Timing 14.1 Absolute Maximum Ratings Storage Temperature Operating Temperature Maximum Junction Temperature Supply Voltage V with Respect Supply Voltage V with Respect Voltage Tolerant Input Pins Voltage on ...
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Recommended Operating Conditions Symbol Parameter Description f Frequency of Operation (SCLK) osc I V Supply Current – MHz (full line rate Supply Current – MHz (full line rate ...
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AC Characteristics and Timing 14.4.1 Typical Reset & Bootstrap Timing Diagram RESIN# RESETOUT# R1 Bootstrap Pins Outputs Figure 10 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# ...
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Reduced Media Independent Interface Figure Characteristics – Reduced media independent Interface (TX) Figure Characteristics – Reduced Media Independent Interface (RX) Symbol Parameter M2 M[3:0]_RXD[1:0] Input Setup Time M3 M[3:0]_RXD[1:0] Input Hold Time M4 ...
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Media Independent Interface Figure Characteristics – Media independent Interface (TX) Figure Characteristics – Media Independent Interface (RX) Symbol Parameter MM2 M[9,3:0]_RXD[3:0] Input Setup Time MM3 Mn_RXD[3:0] Input Hold Time MM4 M[9,3:0]_CRS_DV Input Setup ...
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General Purpose Serial Interface (7-wire) Figure Characteristics – General Purpose Serial Interface (TX) Figure Characteristics – General Purpose Serial Interface (RX) Symbol Parameter SM2 M[3:0]_RXD Input Setup Time SM3 M[3:0]_RXD Input Hold Time ...
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MDIO Input Setup and Hold Timing Figure 17 - MDIO Input Setup and Hold Timing Symbol Parameter D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50404 MDC D1 D2 MDIO MDC D3-max ...
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I²C Input Setup Timing Symbol Parameter S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transistor is controlled by external pullup resistor. ZL50404 SCL S2 S1 ...
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Serial Interface Setup Timing STROBE Datain STROBE Dataout Figure 22 - Serial Interface Output Delay Timing Symbol Parameter D1 DATAIN setup time D2 DATAIN hold time D3 DATAOUT output delay time D4 STROBE low time D5 STROBE high time ...
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JTAG (IEEE 1149.1-2001) TCK TMS, TDI J3-max TDO J3-min Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK ...
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Document Errata 15.1 July 2003 • Initial Release 15.2 November 2003 • Updated Ball Signal Description Table : • clarified the ball signal I/O description for Mn_TXCLK & Mn_RXCLK showing these signals are either inputs OR outputs • clarified ...
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TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN DATE 14Nov02 APPRD. BOTTOM VIEW b Previous package codes MIN MAX Dimension 1. 0.30 0.50 A2 0.53 REF D 16.90 17.10 16.90 17.10 ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...