ZL50404GDC ZARLINK [Zarlink Semiconductor Inc], ZL50404GDC Datasheet - Page 64

• Manufacturer Part Number: ZL50404GDC
• Description: Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.1.3
I²C Address: 014+n; CPU Address:0080+2n (n = port number)
Accessed by CPU and I²C (R/W)
13.3.1.4
I²C Address: 01E+n; CPU Address:0081+2n (n = port number)
Accessed by CPU and I²C (R/W)
Port 0 – 3: (RMAC Ports)
ECR3Pn: Port n Control Register
ECR4Pn: Port n Control Register
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [6:4]
Bit [7]
Bit [0]:
Bit [1]:
Bit [2]:
Bit [4:3]:
Enable receiving short frame < 64B
0: Disable (Default)
1: Allow receiving short frame with correct CRC.
Enable receiving long frame > 1522
0: Disable (Default)
1: Allow receiving long frame that are <= BUF_LIMIT value
Enable pad frame to 64B when transmitted
1: Disable
0: Allow padding to 64B (Default)
Enable compress preamble
1: Only one byte preamble+SFD
0: Send standard preamble (Default)
Number of bytes removed from the IFG. (Default 0)
Link Heart Beat Transmit (RMAC ports only)
0: Disable (Default)
1: Enable
Enable TXCLK output. Active high
0: Disable (Default)
1: Mn_TXCLK pin becomes output in GPSI or MII mode
Enable RXCLK output. Active high
0: Disable (Default)
1: Mn_RXCLK pin becomes output in GPSI or MII mode
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Interface mode:
00 - GPSI mode
01 - MII mode
10 - Reserved
11 - RMII mode (Default)
Zarlink Semiconductor Inc.
ZL50404
64
Data Sheet