ZL50404GDC ZARLINK [Zarlink Semiconductor Inc], ZL50404GDC Datasheet - Page 98

• Manufacturer Part Number: ZL50404GDC
• Description: Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.9.14
Accessed by CPU (R/W)
W0 – QOSC36[7:0] – TOKEN_LIMIT_C00 (CPU Address 8A4)
W1 – QOSC37[7:0] – TOKEN_LIMIT_C01 (CPU Address 8A5)
W2 – QOSC38[7:0] – TOKEN_LIMIT_C02 (CPU Address 8A6)
W3 – QOSC39[7:0] – TOKEN_LIMIT_C03 (CPU Address 8A7)
QOSC36 through QOSC39 represents one set of token limit on the shaper of MMAC port. The granularity of the
numbers is 64 bytes. The shaper is implemented as leaky bucket and the limit here works as bucket size. Since the
hardware implementation can keep negative number, the limit can be as small as one and still can transmit
oversized frame, as long as one byte token is available.
13.3.10
NOTE: Device Manufacturing test registers.
13.3.10.1
CPU Address E00
Accessed by CPU (R/W)
Test group selection for testout[7:0].
13.3.10.2
CPU Address E01
Accessed by CPU (R/W)
Test group selection for testout[15:8].
13.3.10.3
CPU Address E02, E03
Accessed by CPU (RO)
13.3.10.4
CPU Address E10-E14
Accessed by CPU (R/W)
Disable timeout reset on selected state machine status.
See Programming Timeout Reset application note, ZLAN-41, for more information.
(Group E Address) System Diagnostic
QOSC36 - QOSC39 - Shaper Control Port MMAC
DTSRL – Test Output Selection
DTSRM – Test Output Selection
TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8]
MASK0-MASK4 – Timeout Reset Mask
Zarlink Semiconductor Inc.
ZL50404
98
Data Sheet